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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
Preliminary Product Specification
PS003807-1002
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126-3432 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
532 Race Street San Jose, CA 95126-3432 Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
(c) 2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input/Output and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User-Programmable Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 2 3 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Central Processing Unit (CPU) Description . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory (ROM/OTP and RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registers (Grouped by Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 52 54 55 85 85 85 86 89 90
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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List of Figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 48-Pin SSOP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 40-Pin DIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 28-Pin SOIC/DIP Pin Assignment--User Mode . . . . . . . . . . . . . . . . 7 Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Standard Z8 Register File (Working Reg. Groups 0-F, Bank 0) . . . 13 Z8 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . 14 Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 External Interrupt Sources IRQ0-IRQ2 Block Diagram . . . . . . . . . . 17 IRQ Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 General Input/Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Low-Pass Filter (with 8-MHz Crystal) . . . . . . . . . . . . . . . . . . . . . . . 30 Active Glitch/Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 I-V Characteristics for the Current Sink Pad P43 . . . . . . . . . . . . . . 34 T1 Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Counter/Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Starting the Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer Mode Register TOUT Operation . . . . . . . . . . . . . . . . . . . . . . . 40 Counter/Timer Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . 41 Internal Clock Output Using TOUT . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Timer Mode Register TIN Operation . . . . . . . . . . . . . . . . . . . . . . . . 42 Prescaler 1 TIN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Counter/Timer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48-Pin SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
50 86 91 92 92 93
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List of Tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Z86L99/Z86D99 Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 15 Interrupt Edge Select for External Interrupts . . . . . . . . . . . . . . . . . . 17 Control and Status Register Reset Conditions . . . . . . . . . . . . . . . . 20 Clock Status in Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Special Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Active Glitch/Filter Specifications (Preliminary) . . . . . . . . . . . . . . . . 32 Current Sink Pad P43 Specifications (Preliminary) . . . . . . . . . . . . . 33 I/O Port Registers (Group 0, Bank 0, Registers 0-F) . . . . . . . . . . . 52 Timer Control Registers (Group 0, Bank D, Registers 0-F) . . . . . . 53 Control and Status Registers (Group F, Bank 0, Registers 0-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SMR and Port Mode Registers (Group 0, Bank F, Registers 0-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Register Description Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FLAGS Register [Group/Bank F0h, Register C (R252)] . . . . . . . . . 57 RP Register [Group/Bank F0h, Register D (R253)] . . . . . . . . . . . . . 58 SP Register [Group/Bank F0h, Register F (R255)] . . . . . . . . . . . . . 59 LB Register (Group/Bank 0Dh, Register C) . . . . . . . . . . . . . . . . . . . 60 ADCCTRL Register (Group/Bank 0Fh, Register 8) . . . . . . . . . . . . . 61 ADCDATA Register (Group/Bank 00h, Register 7) . . . . . . . . . . . . . 62 IMR (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . . . . . . . . . 63 IPR (Group/Bank 0Fh, Register 9) . . . . . . . . . . . . . . . . . . . . . . . . . 64 IRQ (Group/Bank 0Fh, Register A) . . . . . . . . . . . . . . . . . . . . . . . . . 65 P456CON Register (Group/Bank 0Fh, Register 0) . . . . . . . . . . . . . 67 P3M Register [Group/Bank F0h, Register 7 (R247)] . . . . . . . . . . . . 68 P2 Register [Group/Bank 00h, Register 2 (R2)] . . . . . . . . . . . . . . . 68 P2M Register [Group/Bank F0h, Register 6 (R246)] . . . . . . . . . . . . 68 P4 Register [Group/Bank 00h, Register 4 (R4)] . . . . . . . . . . . . . . . 69 P4M Register (Group/Bank 0Fh, Register 2) . . . . . . . . . . . . . . . . . . 69 P5 Register [Group/Bank 00h, Register 5 (R5)] . . . . . . . . . . . . . . . 70 P5M Register (Group/Bank 0Fh, Register 4) . . . . . . . . . . . . . . . . . . 70 P6 Register [Group/Bank 00h, Register 6 (R6)] . . . . . . . . . . . . . . . 71
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Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57.
P6M Register (Group/Bank 0Fh, Register 6) . . . . . . . . . . . . . . . . . . T1 Register [Group/Bank F0h, Register 2 (R242)] . . . . . . . . . . . . . TMR Register [Group/Bank F0h, Register 1 (R241)] . . . . . . . . . . . . PRE1 Register [Group/Bank F0h, Register 3 (R243)] . . . . . . . . . . . CTR1 Register (In Transmit Mode) (Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTR1 Register (in Demodulation Mode) (Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CTR3 Register (Group/Bank 0Dh, Register 3) . . . . . . . . . . . . . . . . CTR0 Register (Group/Bank 0Dh, Register 0) . . . . . . . . . . . . . . . . HI8 Register (Group/Bank 0Dh, Register B) . . . . . . . . . . . . . . . . . . LO8 Register (Group/Bank 0Dh, Register A) . . . . . . . . . . . . . . . . . . TC8H Register (Group/Bank 0Dh, Register 5) . . . . . . . . . . . . . . . . TC8L Register (Group/Bank 0Dh, Register 4) . . . . . . . . . . . . . . . . . CTR2 Register (Group/Bank 0Dh, Register 2) . . . . . . . . . . . . . . . . HI16 Register (Group/Bank 0Dh, Register 9) . . . . . . . . . . . . . . . . . LO16 Register (Group/Bank 0Dh, Register 8) . . . . . . . . . . . . . . . . . TC16H Register (Group/Bank 0Dh, Register 7) . . . . . . . . . . . . . . . TC16L Register (Group/Bank 0Dh, Register 6) . . . . . . . . . . . . . . . . SMR Register (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . P2SMR Register (Group/Bank 0Fh, Register 1) . . . . . . . . . . . . . . . P5SMR Register (Group/Bank 0Fh, Register 5) . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics for the Z86D99X (OTP Only) . . . . . . . . . . . . . . DC Characteristics for the Z86L99X (Mask Only) . . . . . . . . . . . . . . Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71 72 72 73 74 75 76 77 78 78 79 79 80 81 81 82 82 83 84 84 85 87 88 89 90
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Architectural Overview
The Z86D99 is a low-voltage general-purpose one-time programmable (OTP) Z8(R) microcontroller with an integrated four-channel 8-bit sigma delta analog-to-digital converter. The Z86L99 is the read-only memory (ROM) version of this controller. The Z86D99/Z86L99 family is designed to be used in a wide variety of embedded control applications including battery chargers, home appliances, infrared (IR) remote controls, security systems, and wireless keyboards. It has three counter/timers, a general-purpose 8-bit counter/timer with a 6-bit prescaler and an 8-bit/16-bit counter/timer pair that can be used individually for general-purpose timing or as a pair to automate the generation and reception of complex pulses or signals. Unique features of the Z86D99/Z86L99 family of products include 489 bytes of general-purpose random-access memory (RAM), 256 bytes of which are mapped into the program memory space and can be used to store data variables or as executable RAM, a low-battery detection flag, and a controlled current output pin, which is a regulated current source that sinks a predefined current (ICCO). Table 1 highlights the basic product features of these microcontrollers.
Table 1. Z86L99/Z86D99 Feature Comparison Pins Z86D990 Z86D991 Z86L990 Z86L991 Z86L996 Z86L997 40/48 28 40/48 28 28 28 I/O 32 24 32 24 24 24 Memory (Bytes) 32K OTP 32K OTP 16K ROM 16K ROM 4K ROM 8K ROM Operating Voltage (V) 3.0-5.5 3.0-5.5 2.3-5.5 2.3-5.5 2.3-5.5 2.3-5.5 ADC 4 channel -- 4 channel -- -- -- Timers 3 3 3 3 3 3 Watch-Dog Timer Yes Yes Yes Yes Yes Yes
The Z8 microcontroller core offers more flexibility and performance than accumulator-based microcontrollers. All 256 general-purpose registers, including dedicated input/output (I/O) port registers, can be used as accumulators. This unique register-to-register architecture avoids accumulator bottlenecks for high code efficiency. The registers can be used as address pointers for indirect addressing, as index registers, or for implementing an on-chip stack. The Z8 has a sophisticated interrupt structure and automatically saves the program counter and status flags on the stack for fast context-switching. Speed of execution and smooth programming are also supported by a "working register area" with short 4-bit register addresses.
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The Z8 instruction set, consisting of 43 basic instructions, is optimized for highcode density and reduced execution time. It is similar in form to the ZiLOG Z80 instruction set. The eight instruction types and six addressing modes together with the ability to operate on bits, 4-bit nibbles or binary coded decimal (BCD) digits, 8-bit bytes, and 16-bit words, make for a code-efficient, flexible microcontroller.
Features * * * *
Four-channel, 8-bit sigma delta analog-to-digital (A/D) converter with external voltage references (not available in the 28-pin configuration) Two independent analog comparators Controlled current output 489 bytes of RAM - 233 bytes of general-purpose register-based RAM - 256 bytes of RAM mapped into the program memory space that can be used as data RAM or executable RAM 32 Kbytes of OTP memory (Z86D99X) 16 Kbytes of ROM (Z86L99X)
* * *
Counter/Timers
Special architecture to automate generation and reception of complex pulses or signals: - Programmable 8-bit counter/timer (T8) with two 8-bit capture registers and two 8-bit load registers - Programmable 16-bit counter/timer (T16) with one 16-bit capture register pair and one 16-bit load register pair - Programmable input glitch filter for pulse reception One general-purpose 8-bit counter/timer (T1) with 6-bit prescaler
* * * *
Input/Output and Interrupts
Thirty-two I/Os, twenty-nine of which are bidirectional I/Os with programmable resistive pull-up transistors (24 I/Os are available in the 28-pin configuration) Sixteen I/Os are selectable as stop-mode recovery sources Six interrupt vectors with nine interrupt sources - Three external sources - Two comparator interrupts
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- -
Three timer interrupts One low-battery detector flag
Operating Characteristics
* * * *
8-MHz operation 3.0 V to 5.5 V operating voltage (Z86D990/Z86D991) 2.3 V to 5.5 V operating voltage (Z86L990/Z86L991) Low power consumption with three standby modes: - Stop - Halt - Low Voltage Standby Low-battery detection flag Low-voltage protection circuit (also known as VBO, or voltage brownout, circuit) Watch-dog timer and power-on reset circuits
* * * * * * * * * * * * * *
User-Programmable Option Bits
Clock source--RC/other (LC, resonator, or crystal) Watch-dog timer permanently enable 32-kHz crystal Port 20-27 pull-up resistive transistor Port 40-42 pull-up resistive transistor Port 44-47 pull-up resistive transistor Port 50-51 pull-up resistive transistor Port 54-57 pull-up resistive transistor Port 60-63 pull-up resistive transistor (not available in Z86D991/Z86L991) Port 64-67 pull-up resistive transistor (not available in Z86D991/Z86L991) P43 high impedance in STOP mode (available in OTP only) Force P43 to output a 1 in the open-drain configuration
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Functional Block Diagram
Figure 1 shows the functional block diagram for the microcontrollers.
Register File 256 x 8-bit Expanded Register File
8 7 Port 2 0 Program Memory Power Filter VDD_padring*** VDD_CORE
256 Bytes P52 P53 CIN2 CREF2 Two Analog Comparators
Z8 Core
7 Port 4 0
Machine Timing and Instruction Control
XTAL 1 XTAL 2
*
CIN1 CREF1 P51 P50 7 Port 5 0 7 Port 6 ** 0 *Controlled Current Output **P6 is only in the Z86L990/Z86D990. ***In the 28-pin package, VDD_padring and VDD_CORE are bonded together. Figure 1. Functional Block Diagram 8-Bit C/T (Carrier)
8
Controlled Current Output
P43
16-Bit C/T (Modulation)
8-Bit C/T (General) ADC0/P44 ADC1/P45 ADC2/P46 ADC3/P47
8-Bit A/D VRef+ VRef-
MUX
ADC is only in the Z86L990/Z86D990. Program memory is as follows: Z86D990 32K OTP Z86D991 32K OTP Z86L990 16K ROM Z86L991 16K ROM
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Pin Descriptions
Figure 2 through Figure 4 show the pin names and locations.
P62 P63 P25 P26 P27 NC AVSS VREFP44 P45 P46 P47 VREF+ AVDD VDD_CORE VDD_padring XTAL2 XTAL1 NC P51 P52 P53 P54 P64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Z86D990/ Z86L990
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 281 27 26 25
P61 P60 P24 P23 P22 NC NC P21 P20 P43 VSS VSS P42 P41 P40 P50 P56 NC NC P57 P55 P67 P66 P65
Notes:
1. Both VSS pins must be connected to ground. 2. NC is no connection to the die. 3. AVDD must be connected to VDD_CORE and a 10-F capacitor for good A/D conversion. 4. Power must be connected to VDD_padring. Current passes to VDD_CORE through the internal power filter.
Figure 2. 48-Pin SSOP Pin Assignments
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P62 P63 P25 P26 P27 AVSS VRef- P44/ADC0 P45/ADC1 P46/ADC2 P47/ADC3 VRef+ AVDD/VDD_CORE VDD_padring XTAL2 XTAL1 P51/CIN1/Captive Timer Input P52/CIN2/T1 Timer Input (TIN) P53/CREF2 P54/COUT1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Z86D990/ Z86L990
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
P61 P60 P24 P23 P22 P21 P20 P43/Combined T8 T16 Output
VSS
P42 P41/T16 Output P40/T8 Output P50/CREF1 P56/T1 Timer Output P57 P55/COUT2 P67 P66 P65 P64
Notes:
1. AVDD must be connected to VDD_CORE and a 10-F capacitor for good A/D conversion. 2. Power must be connected to VDD_padring. Current passes to VDD_CORE through the internal power filter.
Figure 3. 40-Pin DIP Pin Assignment
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P25 P26 P27 P44/ADC0 P45/ADC1 P46/ADC2 P47/ADC3 VDD* XTAL2 XTAL1 P51/CIN1/Capture Timer Input P52/CIN2/T1 Timer Input P53/CREF2 P54/COUT1
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Z86D991/ Z86L991
28 27 26 25 24 23 22 21 20 19 18 17 16 15
P24 P23 P22 P21 P20 P43/Combined T8 T16 Output VSS** P42 P41/T16 Output P40/T8 Output P50/CREF1 P56/T1 Timer Output P57 P55/COUT2
Notes:
1. P43 is a controlled current output. 2. P54, P55, P56, and P57 are high drive outputs. * VDD = VDD_CORE + VDD_padring + AVDD
Figure 4. 28-Pin SOIC/DIP Pin Assignment--User Mode
Pins Configuration
Table 2 describes the pins.
Table 2. Pin Descriptions Pin # 28 PDIP/SOIC 24 25 26 27 28 1 2 3 19 40 PDIP 34 35 36 37 38 3 4 5 29 48 SSOP 40 41 44 45 46 3 4 5 34
Symbol P20 P21 P22 P23 P24 P25 P26 P27 P40
Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O
Description Port 2 Bit 0 Port 2 Bit 1 Port 2 Bit 2 Port 2 Bit 3 Port 2 Bit 4 Port 2 Bit 5 Port 2 Bit 6 Port 2 Bit 7 Port 4 Bit 0, T8 Output
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Table 2. Pin Descriptions (Continued) Pin # 28 40 48 Symbol PDIP/SOIC PDIP SSOP Direction Description P41 20 30 35 I/O Port 4 Bit 1, T16 Output P42 21 31 36 I/O Port 4 Bit 2 P43 23 33 39 Output T8/T16 Output, Controlled current output P44 4 8 9 I/O Port 4 Bit 4, A/D Channel 0* P45 5 9 10 I/O Port 4 Bit 5, A/D Channel 1* P46 6 10 11 I/O Port 4 Bit 6, A/D Channel 2* P47 7 11 12 I/O Port 4 Bit 7, A/D Channel 3* P50, CREF1 18 28 33 I/O Port 5 Bit 0, Comparator 1 reference P51, CIN1 11 17 20 I/O Port 5 Bit 1, Capture timer input, IRQ2 P52, CIN2 12 18 21 Input Port 5 Bit 2, Timer 1 timer input, IRQ0 P53, CREF2 13 19 22 Input Port 5 Bit 3, Comparator 2 reference, IRQ1 P54 14 20 23 I/O Port 5 Bit 4, High drive output P55 15 25 28 I/O Port 5 Bit 5, High drive output P56 17 27 32 I/O Port 5 Bit 6, Timer 1 output, High drive output P57 16 26 29 I/O Port 5 Bit 7, High drive output P60 39 47 I/O Port 6 Bit 0 P61 40 48 I/O Port 6 Bit 1 P62 1 1 I/O Port 6 Bit 2 P63 2 2 I/O Port 6 Bit 3 P64 21 24 I/O Port 6 Bit 4 P65 22 25 I/O Port 6 Bit 5 P66 23 26 I/O Port 6 Bit 6 P67 24 27 I/O Port 6 Bit 7 XTAL1 10 16 18 Input Crystal, Oscillator clock XTAL2 9 15 17 Output Crystal, Oscillator clock AVDD 13 14 Analog power supply VDD_CORE 13 15 Z8 core power supply 6 7 Analog ground AVSS VRef- 7 8 Input A/D converter lower reference VRef+ 12 13 Input A/D converter upper reference 8** 14 16 Power supply (pad ring) VDD_padring VSS 22** 32 37, 38 Ground Notes: *A/D converter is not available in the 28-pin configuration. **In the 28-pin configuration, all three (core, pad ring, and analog) powers are tied together.
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Operational Description
Central Processing Unit (CPU) Description
The Z8 architecture is characterized by a flexible I/O scheme, an efficient register and address space structure and a number of ancillary features for cost-sensitive, high-volume embedded control applications. ROM-based products are geared for high-volume production (where the software is stable) and one-time programmable equivalents for prototyping as well as volume production where time to market or code flexibility is critical. Architecture Type The Z8 register-oriented architecture centers around an internal register file composed of 256 consecutive bytes, known as the standard register file. The standard register file consists of 4 I/O port registers (R2, R4, R5, and R6), 12 control and status registers, 233 general-purpose registers, and 7 registers reserved for future expansion. In addition to the standard register file, the Z86D99/Z86L99 family uses 21 control and status registers located in the Z8 expanded register file. Any general-purpose register can be used as an accumulator and address pointer or an index, data, or stack register. All active registers can be referenced or modified by any instruction that accesses an 8-bit register, without the requirement for special instructions. Registers accessed as 16 bits are treated as even-odd register pairs. In this case, the data's most significant byte (MSB) is stored in the even-numbered register, while the least significant byte (LSB) goes into the next higher odd-numbered register. The Z8 CPU has an instruction set designed for the large register file. The instruction set provides a full compliment of 8-bit arithmetic and logical operations. BCD operations are supported using a decimal adjustment of binary values, and 16-bit quantities for addresses and counters can be incremented and decremented. Bit manipulation and Rotate and Shift instructions complete the data-manipulation capabilities of the Z8 CPU. No special I/O instructions are necessary because the I/O is mapped into the register file. CPU Control Registers The standard Z8 control registers govern the operation of the CPU. Any instruction which references the register file can access these control registers. The following are available control registers:
* * *
Register Pointer (RP) Stack Pointer (SP) Program Control Flags (FLAGS)
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* * *
Interrupt Control (IPR, IMR, and IRQ) Stop Mode Recovery (SMR, P2SMR, and P5SMR) Low-Battery Detect (LB) Flag
The Z8 uses a 16-bit Program Counter (PC) to determine the sequence of current program instructions. The PC is not an addressable register. Peripheral registers are used to transfer data, configure the operating mode, and control the operation of the on-chip peripherals. Any instruction that references the register file can access the peripheral registers. The following are peripheral control registers:
* * * * * * * * * *
Analog/Digital Converter (ADCCTRL and ADCDATA) T1 Timer/Counter (TMR, T1, and PRE1) T8 Timer/Counter (CTR0, HI8, LO8, TC8H, and TC8L) T16 Timer/Counter (CTR2, HI16, LO16, TC16H, and TC16L) T8/T16 Control Registers (CTR1and CTR3)
In addition, the four port registers are considered to be peripheral registers. The following are port control registers: Port Configuration Registers (P456CON and P3M) Port 2 Control and Mode Registers (P2 and P2M) Port 4 Control and Mode Registers (P4 and P4M) Port 5 Control and Mode Registers (P5 and P5M) Port 6 Control and Mode Registers (P6 and P6M)
The functions and applications of the control and peripheral registers are explained in "Control and Status Registers" on page 52.
Memory (ROM/OTP and RAM)
There are four basic address spaces available to support a wide range of configurations:
* * * *
Program memory (on-chip) Standard register file Expanded register file Executable RAM
The Z8 standard register file totals up to 256 consecutive bytes organized as 16 groups of 16 eight-bit registers. These registers consist of I/O port registers,
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general-purpose RAM registers, and control and status registers. Every RAM register acts like an accumulator, speeding instruction execution and maximizing coding efficiency. Working register groups allow fast context switching. The standard register file of the Z8 (known as Bank 0) has been expanded to form 16 expanded register file (ERF) banks. The expanded register file allows for additional system control registers and for the mapping of additional peripheral devices into the register area. Each ERF bank can potentially consist of up to 256 registers (the same amount as in the standard register file) that can then be divided into 16 working register groups. Currently, only Group 0 of ERF Banks F and D (0Fh and 0Dh) has been implemented. In addition to the standard program memory and the RAM register files, the Z86D99/Z86L99 family also has 256 bytes of executable RAM that has been mapped into the upper 256 bytes of the program memory address space (FF00h- FFFFh). Data can be written to the executable RAM by using the LDC instruction. Program Memory Structure The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts (IRQ0 through IRQ5.) Address 12 (0Ch) up to 32,767 (7FFFh) consists of on-chip one-time programmable memory. The Z86L99X only has the 4K/8K/16K ROM size. After any reset operation (power-on reset, watch-dog timer time out, and stop mode recovery), program execution resumes with the initial instruction fetch from location 000Ch. After a reset, the first routine executed must be one that initializes the control registers to the required system configuration. A unique feature of the Z86D99/Z86L99 family is the presence of 256 bytes of onchip executable RAM. This random-access memory is in addition to the standard Z8 register file memory available on all Z8 microcontrollers. As illustrated in Figure 5, the executable RAM is mapped into the upper 256 bytes of the 64K program memory address space (FF00h-FFFFh). Data can be written to the executable RAM by using the LDC instruction. Memory locations between 8000h and FEFFh have not been implemented on the Z86D99X microcontrollers. The Z86D99/Z86L99 family does not have the capability of accessing external memory.
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Location (Hex) FFFF 256 bytes Executable RAM FF00 Not Implemented 3FFF/7FFF (ROM)/(OTP) PROGRAM MEMORY Location of the first byte of the initial instruction executed after RESET IRQ5 (lower byte) IRQ5 (upper byte) IRQ4 (lower byte) IRQ4 (upper byte) IRQ3 (lower byte) IRQ3 (upper byte) IRQ2 (lower byte) IRQ2 (upper byte) IRQ1 (lower byte) IRQ1 (upper byte) IRQ0 (lower byte) IRQ0 (upper byte)
000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000
Figure 5. Program Memory Map
Z8 Standard Register File (Bank 0) Bank 0 of the Z8 expanded register file architecture is known as the standard register file of the Z8. As shown in Figure 6, the Z8 standard register file consists of 16 groups of sixteen 8-bit registers known as Working Register (WR) groups. Working Register Group F contains various control and status registers. The lower half of Working Register Group 0 consists of I/O port registers (R0 to R7), the upper eight registers are available for use as general-purpose RAM registers. Working Register Group 1 through Group E of the standard register file are available to be used as general-purpose RAM registers. The user can use 233 bytes of general-purpose RAM registers in the standard Z8 register file (Bank 0).
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Grp/Bnk (F0h) (E0h) (D0h) (C0h) (B0h) (A0h) (90h) (80h) (70h) (60h) (50h) (40h) (30h) (20h) (10h) (00h)
Reg r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r0 to 15 r8 to 15 r0 to 7
Working Register Group Function Control and Status Registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers General-purpose RAM registers I/O Port Registers
Figure 6. Standard Z8 Register File (Working Reg. Groups 0-F, Bank 0)
Z8 Expanded Register File In addition to the Standard Z8 Register File (Bank 0), Expanded Register File Banks F and D of Working Register Group 0 have been implemented on the Z86D99/Z86L99. Figure 7 illustrates the Z8 Expanded Register File architecture. These two expanded register file banks of Working Register Group 0 provide a total of 32 additional RAM control and status registers. The Z86D99/Z86L99 family has implemented 21 of the 32 available registers.
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Z8 Standard Register File
F E D C B A 9 8 7 6 5 4 3 2 1 0 Control and Status Reg.
Z8 Expanded Register Files
Group 0, Bank F
General-Purpose RAM Registers
Stop Mode Recovery and Port Mode Registers
Working Register Groups
Bank F Group 0, Bank D
I/O Port Registers Bank 0
Banks 2 through C are Reserved--Not Implemented (Bank E is also reserved)
Timer Control Registers
Figure 7. Z8 Expanded Register File Architecture
Clock Circuit Description
The Z8 derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping circuit, and a clock buffer. The oscillator's input is XTAL1, and the oscillator's output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock, RC, or an external clock source. Clock Control The Z8 offers software control of the internal system clock using programming register bits in the SMR register. This register selects the clock divide value and determines the mode of STOP Mode Recovery. The default setting is external clock divide-by-two. When bits 1 and 0 of the SMR register are set to 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal to the external clock frequency divided by two. When bit 1 of the SMR register is set to 1, then SCLK and TCLK equal the external clock frequency. Refer to Table 53 on page 85 for the maximum clock frequency. A divide-by-16 prescaler of SCLK and TCLK allows the user to selectively reduce device power consumption during normal processor execution (under SCLK control) and/or HALT mode, where TCLK sources counter/timers and interrupt logic. Combining the divide-by-two circuitry with the divide-by-16 prescaler allows the external clock to be divided by 32.
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Interrupts
The Z86D99/Z86L99 family allows up to six different interrupts, three external and three internal, from nine possible sources. The six interrupts are assigned as follows:
* * * *
Three edge-triggered external interrupts (P51, P52, and P53), two of which are shared with the two analog comparators One internal interrupt assigned to the T8 Timer One internal interrupt assigned to the T16 Timer One internal interrupt shared between the Low-Battery Detect flag and the T1 Timer
Table 3 presents the interrupt types, the interrupt sources, and the location of the specific interrupt vectors.
Table 3. Interrupt Types, Sources, and Vectors Name IRQ0 Vector Location Comments 0,1 External interrupt (P52) is triggered by either rising or falling edge; internal interrupt generated by Comparator 2 is mapped into IRQ0 P53 (F) 2,3 External interrupt (P53) is triggered by a falling edge P51 (R/F), Comparator 1 4,5 External interrupt (P51) is triggered by either a rising or falling edge; internal interrupt generated by Comparator 1 is mapped into IRQ2 T16 Timer 6,7 Internal interrupt T8 Timer 8,9 Internal interrupt LVD, T1 Timer 10,11 Internal interrupt, LVD flag is multiplexed with T1 Timer End-ofCount interrupt F = Falling-edge triggered; R = Rising-edge triggered. When LVD is enabled, IRQ5 is triggered only by low-voltage detection. Timer 1 does not generate an interrupt. Source P52 (F/R), Comparator 2
IRQ1 IRQ2
IRQ3 IRQ4 IRQ5
Notes:
These interrupts can be masked and their priorities set by using the Interrupt Mask Register (IMR) and Interrupt Priority Register (IPR) (Figure 8.) When more than one interrupt is pending, priorities are resolved by a priority encoder, controlled by the IPR.
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EI Instruction S Interrupt Request Register (IRQ,FAH)
R Reset Power-On Reset (POR) Figure 8. Interrupt Block Diagram
Interrupt requests are stored in the Interrupt Request Register (IRQ), which can also be used for polling. When an interrupt request is granted, the Z8 enters an "interrupt machine cycle" that globally disables all other interrupts, saves the program counter (the address of the next instruction to be executed) and status flags, and finally branches to the vector location for the interrupt granted. It is only at this point that control passes to the interrupt service routine for the specific interrupt. All six interrupts can be globally disabled by resetting the master Interrupt Enable (bit 7 of the IMR) with a Disable Interrupts (DI) instruction. Interrupts are globally enabled by setting the same bit with an Enable Interrupts (EI) instruction. Descriptions of three interrupt control registers--the Interrupt Request Register, the Interrupt Mask Register, and the Interrupt Priority Register--are provided in "Register Summary" on page 52. The Z8 family supports both vectored and polled interrupt handling. External Interrupt Sources External sources involve interrupt request lines P51, P52, and P53 (IRQ2, IRQ0, and IRQ1, respectively.) IRQ0, IRQ1, and IRQ2 are generated by a transition on the corresponding port pin. As shown in Figure 9, when the appropriate port pin (P51, P52, or P53) transitions, the first flip-flop is set. The next two flip-flops synchronize the request to the internal clock and delay it by two internal clock periods. The output of the most recent flip-flop (IRQ0, IRQ1, or IRQ2) sets the corresponding Interrupt Request Register bit.
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Figure 9. External Interrupt Sources IRQ0-IRQ2 Block Diagram
The programming bits for the Interrupt Edge Select function are located in the IRQ register, bits 6 and 7. The configuration of these bits and the resulting interrupt edge is shown in Table 4.
Table 4. Interrupt Edge Select for External Interrupts Interrupt Request Register Bit 7 Bit 6 0 0 0 1 1 0 1 1 Interrupt Edge IRQ2 (P51) IRQ0 (P52) Falling Falling Falling Rising Rising Falling Rising/Falling Rising/Falling
Note: Although interrupts are edge triggered, minimum interrupt request Low and High times must be observed for proper operation. See "Electrical Characteristics" on page 85 for exact timing requirements (TWIL, TWIH) on external interrupt requests. Internal Interrupt Sources Internal sources are ORed with the external sources, so that either an internal or external source can trigger the interrupt. Interrupt Request Register Logic and Timing Figure 10 shows the logic diagram for the Interrupt Request Register. The leading edge of an interrupt request sets the first flip-flop. It remains set until the interrupt requests are sampled.
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Figure 10. IRQ Logic
Internal interrupt requests are sampled during the most recent clock cycle before an Op Code fetch (see Figure 11.) External interrupt requests are sampled two internal clocks earlier than internal interrupt requests because of the synchronizing flip-flops shown in Figure 9.
Figure 11. Interrupt Request Timing
At sample time, the interrupt request is transferred to the second flip-flop shown in Figure 10, which drives the interrupt mask and priority logic. When an interrupt cycle occurs, this flip-flop is reset only for the highest priority level that is enabled. The user has direct access to the second flip-flop by reading and writing to the IRQ. The IRQ is read by specifying it as the source register of an instruction, and the IRQ is written by specifying it as the destination register. Interrupt Initialization After RESET, all interrupts are disabled and must be re-initialized before vectored or polled interrupt processing can begin. The Interrupt Priority Register, Interrupt Mask Register, and Interrupt Request Register must be initialized, in that order, to
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start the interrupt process. However, the IPR does not have to be initialized for polled processing. Interrupts must be globally enabled using the EI instruction. Setting bit 7 of the IMR is not sufficient. Subsequent to this EI instruction, interrupts can be enabled either by IMR manipulation or by use of the EI instruction, with equivalent effects. Additionally, interrupts must be disabled by executing a DI instruction before the IPRs or IMRs can be modified. Interrupts can then be enabled by executing an EI instruction. IRQ Software Interrupt Generation IRQ can be used to generate software interrupts by specifying IRQ as the destination of any instruction referencing the Z8 Standard Register File. These Software Interrupts (SWIs) are controlled in the same manner as hardware-generated requests (the IPR and the IMR control the priority and enabling of each SWI level). To generate a SWI, the request bit in the IRQ is set as follows:
OR IRQ, #NUMBER
where the immediate data, NUMBER, has a 1 in the bit position corresponding to the appropriate level of the SWI. For example, for an SWI on IRQ5, NUMBER has a 1 in bit 5. With this instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and there are no higher priority pending requests, control is transferred to the service routine pointed to by the IRQ5 vector.
Reset Conditions
A system reset overrides all other operating conditions and puts the Z8 into a known state. The control and status registers are reset to their default conditions after a power-on reset (POR) or a Watch-Dog Timer (WDT) time-out while in RUN mode. The control and status registers are not reset to their default conditions after Stop Mode Recovery (SMR) while in HALT or STOP mode. General-purpose registers are undefined after the device is powered up. Resetting the Z8 does not affect the contents of the general-purpose registers. The registers keep their most recent value after any reset, as long as the reset occurs in the specified VCC operating range. Registers do not keep their most recent state from a VLV reset, if VCC drops below VRAM (see Table 54 on page 87). Following a reset (see Table 5), the first routine executed must be one that initializes the control registers to the required system configuration.
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Table 5. Control and Status Register Reset Conditions Address Register Function Register Pointer Stack Pointer Program Control Flags Low Battery Detect ADC Control ADC Data Interrupt Mask Interrupt Priority Interrupt Request Port Configuration (A) Port Configuration (B) Port 2 Data Port 2 Mode Port 4 Data Port 4 Mode Port 5 Data Port 5 Mode Port 6 Data Port 6 Mode T1 Timer Data T1 Timer Mode T1 Timer Prescale T8/T16 Control (A) T8/T16 Control (B) T8 Timer Control T8 High Capture T8 Low Capture T8 High Load T8 Low Load T16 Timer Control T16 High Capture T16 Low Capture T16 High Load T16 Low Load Grp/Bnk Register
F0h F0h F0h 0Dh 0Fh 00h F0h F0h F0h 0Fh F0h 00h F0h 00h 0Fh 00h 0Fh 00h 0Fh F0h F0h F0h 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh
Reset Value Symbol R/W 7 R/W 0 R/W X R/W X R/W 1 R/W 0 R W 0 0 R/W 0 R/W 0 R/W 0 W W 1 1 R/W X R/W X R/W 1 R/W X R/W 1 R/W X R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 RW
6 0 X X 1 0 0 0 0 0 0 1 X 1 X 1 X 1 X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
5 0 X X 1 0 0 0 0 0 0 1 X 1 X 1 X 1 X 1 0 0 0 0* 0* 0* 0 0 0 0 0 0 0 0 0
4 0 X X 1 0 0 0 0 0 0 1 X 1 X 1 X 1 X 1 0 0 0 0* X 0* 0 0 0 0 0 0 0 0 0
3 0 X X 1 0 0 0 0 0 0 1 X 1 X X 1 X 1 0 0 0 0 X 0* 0 0 0 0 0 0 0 0 0
2 0 X X X 0 0 0 0 0 1 1 X 1 X X 1 X 1 0 0 0 0 X 0* 0 0 0 0 0 0 0 0 0
1 0 X X 0 0 0 0 0 0 1 1 X 1 X 1 X 1 X 1 0 1 0 0 X 0* 0 0 0 0 0 0 0 0 0
0 0 X X 0 0 0 0 0 0 1 1 X 1 X 1 X 1 X 1 0 1 0 0 X 0 0 0 0 0 0 0 0 0 0
r13 (R253) RP r15 (R255) SP r12 (R252) Flags r12 r8 r7 (R7) LB ADCCTRL ADCDATA
r11 (R251) IMR r9 (R249) IPR r10 (R250) IRQ r0 r2 (R2) r4 (R4) r2 r5 (R5) r4 r6 (R6) r6 P456CON P2 P4 P4M P5 P5M P6 P6M r7 (R247) P3M r6 (R246) P2M
1** 1
r2 (R242) T1 r1 (R241) TMR r3 (R243) PRE1 r1 r3 r0 r11 r10 r5 r4 r2 r9 r8 r7 r6 CTR1 CTR3 CTR0 HI8 LO8
0
R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TC8H
TC8L CTR2 HI16

LO16
TC16H TC16L
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Table 5. Control and Status Register Reset Conditions (Continued) Address Register Function Stop Mode Recovery Port 2 SMR Source Port 5 SMR Source
Notes:
Reset Value Symbol SMR P2SMR P5SMR R/W 7 R/W 0 R/W 0 R/W 0 6 0 0 0 5 1 0 0 4 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 r11 r1 r5
Grp/Bnk Register
0Fh 0Fh 0Fh
This register is not reset following Stop Mode Recovery (SMR). *This bit is not reset following SMR. X means this bit is undefined at POR and is not reset following SMR. **In OTP, the default for P43 is open-drain output at power up; you need to initialize the P43 data. In the mask part, the P43 output is disabled until it is configured as output.
Power-On Reset A POR (cold start) always resets the Z8 control and status registers to their default conditions. A POR sets bit 7 of the Stop Mode Recovery register to 0 to indicate that a cold start has occurred. A timer circuit clocked by a dedicated on-board RC oscillator is used for the Power-On Reset Timer (TPOR) function. The POR time is specified as TPOR. TPOR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR delay timer circuit is a one-shot timer triggered by one of three conditions:
* * *
Power Fail to Power OK status including recovery from Low Voltage (VLV) Standby mode STOP-Mode Recovery (when bit 5 of the SMR register = 1) WDT time-out
Under normal operating conditions, a stop mode recovery event always triggers the POR delay timer. This delay is necessary to allow the external oscillator time to stabilize. When using an RC or LC oscillator (with a low Q factor), the shorter wake-up time means the delay can be eliminated. Bit 5 of the SMR register selects whether the POR timer delay is used after StopMode Recovery or is bypassed. If bit 5 =1, then the POR timer delay is used. If bit 5 = 0, then the POR timer delay is bypassed. In this case, the SMR source must be held in the recovery state for 5 TpC to pass the Reset signal internally. Watch-Dog Timer (WDT) The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. When operating in the RUN modes, a WDT reset is functionally
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equivalent to a hardware POR reset. If the mask option of the permanently enabled watch-dog timer is selected, it runs when power up. If the option is not selected, the WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction. The WDT instruction does not affect the Zero (Z), Sign (S), and Overflow (V) flags. Permanently enabled WDTs are always enabled, and the WDT instruction is used to refresh it. The WDT cannot be disabled after it has been initially enabled. The WDT is off during both HALT and STOP modes. The WDT circuit is driven by an on-board RC oscillator. The time-out period for the WDT is fixed to a typical value (see Table 57 on page 90).
Power Management
In addition to the standard RUN mode, the Z8 supports three power-down modes to minimize device current consumption. The following three modes are supported:
* * *
HALT STOP Low-Voltage Standby
Table 6 shows the status of the internal CPU clock (SCLK), the internal Timer clock (TCLK), the external oscillator, and the Watch-Dog Timer during the RUN mode and three low-power modes.
Table 6. Clock Status in Operating Modes Operating Mode SCLK TCLK External OSC RUN On On On HALT Off On On STOP Off Off Off Low-Voltage Standby Off Off Off Note: * When WDT is enabled by the mask option bit WDT* On Off Off Off
Using the Power-Down Modes In order to enter HALT or STOP mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. You can flush the
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instruction pipeline by executing a NOP (Op Code = FFh) immediately before the appropriate sleep instruction. For example: Mnemonic Comment NOP ; clear the pipeline STOP ; enter STOP mode or Mnemonic Comment NOP ; clear the pipeline HALT ; enter HALT mode HALT HALT mode suspends instruction execution and turns off the internal CPU clock (SCLK). The on-chip oscillator circuit remains active, so the internal Timer clock (TCLK) continues to run and is applied to the counter/timers and interrupt logic. An interrupt request, either internally or externally generated, must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction immediately following the HALT. The HALT mode can also be exited by a POR. In this case, the program execution restarts at the reset address 000Ch. STOP STOP mode provides the lowest possible device standby current. This instruction turns off both the internal CPU clock (SCLK) and internal Timer clock (TCLK) and reduces the standby current to the minimum. The STOP mode is terminated by a POR or SMR source. Terminating the STOP mode causes the processor to restart the application program at address 000Ch. Note: When the STOP instruction is executed, the microcontroller goes into the STOP mode despite any state/change of the state of the port. The ports need to be checked immediately before the NOP and STOP instructions to ensure the right input logic before waiting for the change of the ports. Stop Mode Recovery Sources Exiting STOP mode using an SMR source is greatly simplified in the Z86D99/ Z86L99 family. The Z86D99/Z86L99 family of products allows 16 individual I/O Op Code
FFh 7Fh
Op Code
FFh 6Fh
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pins (Ports 2 and 5) to be used as stop-mode recovery sources. The STOP mode is exited when one of these SMR sources is toggled. A transition from either low to high or high to low on any pin of Port 2 or Port 5 if the pin is identified as an SMR source will effect an SMR. There are three registers that control STOP mode recovery:
* * *
Stop Mode Recovery Port 2 Stop Mode Recovery (P2SMR) Port 5 Stop Mode Recovery (P5SMR)
The functions and applications of these registers are explained in "Stop-Mode Recovery Control Registers" on page 82. Low-Voltage Standby An on-chip voltage comparator checks that the VCC level is at the required level for correct operation of the Z8. When VCC falls below the low-voltage trip voltage (VLV), reset is globally driven, and then the device is put in a low-current standby mode with the external oscillator stopped. If the VCC remains above VRAM, the RAM content is preserved. When the power level rises above the VLV level, the device performs a POR and functions normally. The minimum operating voltage varies with temperature and operating frequency, while VLV varies with temperature only.
I/O Ports
The Z86D99/Z86L99 family has up to 32 lines dedicated to input and output in the 40-pin configuration. These lines are grouped into four 8-bit ports known as Port 2, Port 4, Port 5, and Port 6. All four ports are bit programmable as either inputs or outputs with the exception of P52, P53, and P43. P52 and P53 are input only as they are used in OTP programming. P43 is the controlled current output and is therefore output only. All ports have push-pull CMOS outputs. In addition, the push-pull outputs can be turned off for open-drain operation using the P456CON register. Internal resistive pull-up transistors are available as a user-defined OTP/mask option on all ports. For Ports 4, 5, and 6, the pull-ups are nibble selectable. For Port 2, the pull-up option applies to all eight I/O lines. Note: Internal pull-ups are disabled on any given pin or group of port pins when those pins are programmed as outputs.
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Mode Registers Each port has an associated Mode Register that determines the port's functions and allows dynamic change in port functions during program execution. Port and Mode Registers are mapped into the Standard Register File. Because of their close association, Port and Mode Registers are treated like any other general-purpose register. There are no special instructions for port manipulation. Any instruction that addresses a register can address the ports. Data can be directly accessed in the Port Register, with no extra moves. Input and Output Registers Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output register, and associated buffer and control logic. Because there are separate input and output registers associated with each port, writing bits defined as inputs store the data in the output register. This data cannot be read as long as the bits are defined as inputs. However, if the bits are reconfigured as output, the data stored in the output register is reflected on the output pins and can then be read. This mechanism allows the user to initialize the outputs before driving their loads. Because port inputs are asynchronous to the Z8 internal clock, a READ operation could occur during an input transition. In this case, the logic level might be uncertain (somewhere between a logic 1 and 0). General Port I/O The eight I/O lines of each port (except P43, P52, and P53) can be configured under software control to be either input or output, independently. Bits programmed as outputs can be globally programmed as either push-pull or opendrain. See Figure 12.
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Open-Drain I/O
OTP/Mask VCC Option Pull-Up *
Pad
Out
In
Note: * Pull-up resistance is about 200 K at 2.3 V and 75 K at 5.0 V with +50% tolerance. Figure 12. General Input/Output Pin
Read/Write Operations The ports are accessed as general-purpose registers. Port registers are written by specifying the port register as an instruction's destination register. Writing to a port causes data to be stored in the output register of the port, and reflected externally on any bit configured as an output. Ports are read by specifying the port register as the source register of an instruction. When an output bit is read, data on the external pin is returned. Under normal loading conditions, returning data on the external pin is equivalent to reading the output register. However, if a bit is defined as an open-drain output, the data returned is the value forced on the output pin by the external system. This value might not be the same as the data in the output register. Reading input bits also returns data on the external pins.
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Special Functions Table 7 defines the special functions of Ports 4 and 5.
Table 7. Special Port Pin Functions Function Analog Comparator Inputs Analog Comparator References Analog Comparator Outputs ADC Channels Pin P51 P52 P50 P53 P54 P55 P44 P45 P46 P47 P52 P53 P51 P52 P51 P56 P40 P41 P43 P41 P42 Signal CIN1 CIN2 CREF1 CREF2 COUT1 COUT2 ADC0 ADC1 ADC2 ADC3 IRQ0 IRQ1 IRQ2 TIN Demodulator_Input T1OUT P40_Out P41_Out P43_Out DSn Enable ASn Enable Configuration Register P456CON P456CON
External Interrupts
TIN External Clock Input Capture Timer Input T1 Timer Output T8 Output T16 Output Combined T8/T16 Output Controlled Current Output ZiLOG Test Mode
ADCCTRL ADCCTRL ADCCTRL ADCCTRL IMR and IRQ IMR and IRQ IMR and IRQ TMR and PRE1 CTR1 TMR CTR0 CTR2 CTR1 P456CON P456CON
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Peripherals
Analog Comparators The Z86D99/Z86L99 family includes two independent on-chip general-purpose analog comparators as shown in Figure 13. The comparators are multiplexed with a digital input signal by the P456CON register. They can also be used to generate interrupts IRQ0 and IRQ2. The comparators are turned off in STOP mode.
P51 (CIN1) P50 (CREF1)
IRQ2, P51 Data Latch + - Comparator 1 P456CON Bit5 1 = comparator 0 = digital
P52 (CIN2) P53 (CREF2)
IRQ0, P52 Data Latch + - Comparator 2 P456CON Bit4 1 = comparator 0 = digital
Figure 13. Analog Comparators
Analog/Digital Converter (ADC) The Z86D99/Z86L99 family incorporates an 8-bit ADC that uses a sigma delta architecture (Figure 14) comprised of a modulator and a digital filter. The input is selected (bit 3,2 from ADCCTRL) with an analog mux from 4 (P47-P44) pins that can be configured as analog inputs (bit 7-4 from ADCCTRL). Note: Whenever an input pin has an analog value, the digital input buffer has to be disabled in order to reduce the current through the device.
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Figure 14. ADC Block Diagram
The low-pass filter transfer function is presented in Figure 15 with the -3-dB frequency given by the formula:
f 3db = 0.0021 f ADC
where fADC is the sampling frequency of the modulator.
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Filter response 0 2 4 6 8 10 12 14 16 18 20
Out/In[db]
0
0.5
1
1.5
2
2.5 log10(f)
3
3.5
4
4.5
5
Figure 15. Low-Pass Filter (with 8-MHz Crystal)
The sampling frequency of the modulator fADC can be selected between fSCLK and fSCLK/2 (bit1 from ADCCTRL). Reducing the clock frequency lowers the power dissipated in the ADC block. The ADC can be enabled or disabled. When enabled, the converter tracks the input voltage. When switching between the channels (step response), the required time to reach the final value is given by the time constant of the low-pass filter:
2 952 2 T delay = -------- = --------------------------- = ---------0.0021f ADC f ADC f 3db
When available, the reference for the ADC is set externally with the Vref+ and Vrefpins. The output code represents the following ratio:
Vin - V RefD out = ------------------------------ x 256 V Ref+ - V Ref-
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Though the ADC functions for smaller input voltage range (VRef+-VRef-), the noise and offsets remain constant over the specified electrical range. The errors of the converter increase due to small input signals. For fast access to the output of the ADC, the current data is available in the ADC result register (r8, bank00). To reduce the interference between the digital part and the analog part, separate AVSS and AVDD pins are available on the packages where the ADC can be used. Note: In the smaller packages, which do not support the ADC, the user must keep the converter not active in order to not have power dissipated in the ADC block. By default, ADC is off. Active Glitch Filter The Z86D99/Z86L99 family incorporates an active power/glitch filter that can be used to improve the quality of the power supply when the device is operating in noisy environments. The chips use three separate power buses:
* * *
pad ring power bus (all the output drivers plus the crystal/RC oscillator) called VDD_padring core power bus (all digital circuitry) called VDD_CORE analog power bus (all analog circuitry) called AVDD
Depending on the pin availability, one or more of the power buses are connected together. The active power filter can be used in the packages that have the VDD separate. Figure 16 shows the internal schematic.
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Z86D99/Z86L99
Figure 16. Active Glitch/Power Filter
When the internal power/glitch filter is not used, both VDD_padring and VDD_CORE must be connected together externally to the power supply. When the internal circuitry is used, the VDD_padring has to be connected to the power supply and the VDD_CORE has to be connected to an external energy storage capacitor (1-10 F range). The core is connected only to this capacitor during power supply glitches. Table 8 describes the active glitch/filter specifications.
Table 8. Active Glitch/Filter Specifications (Preliminary) Parameter Diff. stage gain Diff. stage bandwidth Rise time Fall time Rdson Max Min 75 dB 15 MHz Condition
VDD_padring
255 ns 214 ns 10
50 mV pulse 50 mV pulse
On the wafer level, all three power buses are available. Depending on the number of pins of the package, one or more power buses are connected together. The active glitch/power filter effectively increases the noise immunity for batteryoperated designs where the controller is driving high current loads (for example, IR LED).
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Controlled Current Output P43 is an open-drain output-only pin on the Z86D990/D991, but it can be configured as output or Tristate High Impedance on the Z86L990/L991. To function properly, Bit 3 of P4M must be set to zero to configure the pin as an open-drain output. For the Z86L990/L991 after reset, P43 defaults to Tristate High Impedance while the Z86D990/D991 P43 is always configured as output. The data at Port 4 must be initialized as it is undefined at power-on reset. The current output is a controlled current source that is controlled by the output of the value of P43 (see Table 9). P43 cannot be configured as input, and if P43 is read, P43 always returns the state of the output value (1 for no sink and 0 for sink). P43 uses internal current reference and will draw current if it outputs a low logic even without external connection. This applies to both Run mode and Stop mode.
Table 9. Current Sink Pad P43 Specifications (Preliminary) Parameter Rise time Fall time Voutmin Comparator response Regulated current Internal resistance 80 mA Min Max 0.4 0.02 0.54 V 0.2 120 mA 80 Conditions LED load LED load @27C
The pad driver can function in two modes:
*
controlled current output, when the voltage on the pad is over a minimum value
V pad > Voutmin
*
resistive pull down when the driver cannot regulate the current; in this mode, the gate of the NMOS pull down is raised to the power rail.
The I-V characteristics of the pad are presented in Figure 17.
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Figure 17. I-V Characteristics for the Current Sink Pad P43
The CPU reads the mode of the pad driver by reading bit number 2 from the LB register. This bit is the output of a Set-Reset flip-flop that sets whenever the voltage on the pad is lower than Voutmin and is reset by a CPU write to the respective register. T1 Timer The Z86D99/Z86L99 family provides one general-purpose 8-bit counter/timer, T1, driven by its own 6-bit prescaler, PRE1. The T1 counter/timer is independent of the processor instruction sequence, which relieves software from time-critical operations such as interval timing and event counting. The T1 counter/timer operates in either single-pass or continuous mode. At the end-of-count, counting either stops or the initial value is reloaded and counting continues. Under software control, new values are loaded immediately or when the end-of-count is reached. Software also controls the counting mode, how the counter/timer is started or stopped, and the counter/timer's use of I/O lines. Both the counter and prescaler registers can be altered while the counter/timer is running.
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Counter/timer 1 is driven by a timer clock generated by dividing the internal clock by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer form a synchronous 16-bit divide chain. Counter/timer T1 can also be driven by an external input (TIN) using Port P52. Port P56 can serve as a timer output (TOUT) through which T1 or the internal clock can be output. The timer output toggles at the end-of-count. Figure 18 is a block diagram of the counter/timer.
OSC
+2
Internal Clock +2 External Clock TOUT P56
Clock Logic +4 6-Bit Down Counter 8-Bit Down Counter
IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write
T1 Initial Value Register
T1 Current Value Register Read
TINP31
Write
Internal Data Bus Figure 18. T1 Counter/Timer Block Diagram
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The counter/timer, prescaler, and associated mode registers are mapped into the register file as shown in Figure 19. The software uses the counter/timer as a general-purpose register, which eliminates the need for special instructions.
DEC Hex identifiers
243 242 241
T1 prescaler Timer/counter 1 Timer mode
F3 PRE1 F2 T1 F1 TMR
Figure 19. Register File
Prescaler and Counter/Timer The prescaler PRE1 (F3h) consists of an 8-bit register and a 6-bit down-counter as shown in Figure 18 on page 35. The prescaler register is a read-write register. Figure 20 shows the prescaler register. R243 PRE1 Prescaler 1 Register (F3h; Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Count mode 1 = T1 modulo-N 0 = T1 single pass Clock source 1 = T1 internal 0 = T1 external (TIN) Prescaler modulo (range: 1-64 decimal, 01h-00h) Figure 20. Prescaler 1 Register
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The six most significant bits (D2-D7) of PRE1 hold the prescaler count modulo, a value from 11 to 64 decimal. The prescaler register also contains control bits that specify T1 counting modes. These bits also indicate whether the clock source for T1 is internal or external. The counter/timer T1 (F2h) consists of an 8-bit down-counter, a write-only register that holds the initial count value, and a read-only register that holds the current count value (see Figure 18 on page 35). The initial value can range from 1 to 256 decimal (01h, 02h, ..., 00h). Figure 21 illustrates the counter/timer register. R242 T1 Counter/Timer 1 Register (F2h; Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
Initial value when written (range 1-256 decimal, 01h-00h) Current value when read Figure 21. Counter/Timer 1 Register
Counter/Timer Operation Under software control, T1 is started and stopped using the Timer Mode register (F1h) bits D2-D3: a Load bit and an Enable Count bit. See Figure 22. R241 TMR Timer Mode Register (F1h; Read/Write)
D3 D2 D1 D0
Reserved 0 = No function 1 = Load T1 0 = Disable T1 count 1 = Enable T1 count Figure 22. Timer Mode Register
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Load and Enable Count Bits Setting the Load bit D2 to 1 transfers the initial values in the prescaler and the counter/timer registers into their respective down-counters. The next internal clock resets bit D2 to 0, readying the Load bit for the next load operation. The initial values can be loaded into the down-counters at any time. If the counter/timer is running, the counter/timer continues to run and starts the count over with the initial value. Therefore, the Load bit actually functions as a software re-trigger. The T1 counter/timer remains at rest as long as the Enable Count bit D3 is 0. To enable counting, the Enable Count bit D3 must be set to 1. Counting actually starts when the Enable Count bit is written by an instruction. The first decrement occurs four internal clock periods after the Enable Count bit has been set. The Load and Enable Count bits can be set at the same time. For example, using the instruction OR TMR #%0C sets both D2 and D3 of TMR to 1. The initial values of PRE1 and T1 are loaded into their respective counters, and the count is started after the M2T2 machine state after the operand is fetched as shown in Figure 23.
M3 M1 M2 Mn
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
#03 is fetched
TMR is written; counter/timers are loaded
first decrement occurs four clocks later
Figure 23. Starting the Count
Prescaler Operations During counting, the programmed clock source drives the prescaler 6-bit counter. The counter is counted down from the value specified by bits D2-D7 of the corresponding prescaler register, PRE0 or PRE1 (Figure 24). When the prescaler counter reaches its end-of-count, the initial value is reloaded and counting continues. The prescaler never actually reaches zero. For example, if the prescaler is set to divide by three, the count sequence is as follows: 3-2-1-3-2-1-3-2...
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R243 PRE1 Prescaler 1 Register (F3h; Read/Write)
D0
Count mode 1 = T1 modulo-N 0 = T1 single pass Figure 24. Counting Modes
When the PRE1 register is loaded with 000000 in the six most significant bits, the prescaler divides by 64. If that number is 000001, the prescaler does not divide and passes its clock on to T1. Each time the prescaler reaches its end-of-count, a carry is generated, which allows the counter/timer to decrement by one on the next timer clock input. When T1 and PRE1 both reach their end-of-count, an interrupt request is generated-- IRQ5 for T1. Depending on the counting mode selected, the counter/timer either comes to rest with its value at 00h (single-pass mode), or the initial value is automatically reloaded and counting continues (continuous mode). In single-pass mode, the prescaler still continues to decrement when the timer T1 has reached its end-of-count. The prescaler always starts from its programmed value upon restarting the counter. The counting modes are controlled by bit D0 of PRE1, with D0 cleared to 0 for single-pass counting mode or set to 1 for continuous mode. The counter/timer can be stopped at any time by setting the Enable Count bit to 0 and restarted by setting the Enable Count bit back to 1. The T1 counter/timer continues its count value at the time it was stopped. The current value in the T1 counter/timer can be read at any time without affecting the counting operation. New initial values can be written to the prescaler or the counter/timer registers at any time. These values are transferred to their respective down-counters on the next load operation. If the counter/timer mode is continuous, the next load occurs on the timer clock following an end-of-count. New initial values must be written before the load operation because the prescaler always effectively operates in continuous count mode. If the value loaded in the T1 register is 01h, the timer is actually not timing or counting at all; the timer is passing the prescaler end-of-count through. Because the prescaler is continuously running, regardless of the single-pass/continuous mode operation, the 8-bit timer continuously times out at the rate of the prescaler end-of-count if the T1 timer value is programmed to 01h.
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The time interval (i) until end-of-count, is given by i=txpxv where t is 8 divided by XTAL frequency, p is the prescaler value (1 - 64), and v is the counter/timer value (1 - 256). The prescaler and counter/timer are true divideby-n counters. TOUT Modes The Timer Mode register TMR (F1h) (Figure 25) is used in conjunction with the Port 5 Mode register P5M to configure P56 for TOUT operation. In order for TOUT to function, P56 must be defined as an output line by setting P5M bit D6 to 0. Output is controlled by one of the counter/timers (T0 or T1) or the internal clock. R241 TMR Timer Mode Register (F1h; Read/Write)
D7 D6 D2
0 = No function 1 = Load T1 TOUT modes TOUT off = 00 Reserved = 01 T1 out = 10 Internal clock out = 11 Figure 25. Timer Mode Register TOUT Operation
The P56 output is selected by TMR bits D7 and D6. T1 is selected by setting D7 and D6 to 1 and 0, respectively. The counter/timer TOUT mode is turned off by setting TMR bits D7 and D6 both to 0, freeing P36 to be a data output line. TOUT is initialized to a logic 1 whenever the TMR Load bit D2 is set to 1. At end-of-count, the interrupt request line IRQ5 clocks a toggle flip-flop. The output of this flip-flop drives the TOUT line P56. In all cases, when the counter/timer reaches its end-of-count, TOUT toggles to its opposite state (see Figure 26). If, for example, the counter/timer is in continuous counting mode, TOUT has a 50% duty cycle output. You can control the duty cycle by varying the initial values after each end-of-count.
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+2 IRQ5 (T1 end-of-count)
P56
TOUT
Figure 26. Counter/Timer Output Using TOUT
The internal clock can be selected as output instead of T1 by setting TMR bits D7 and D6 both to 1. The internal clock (XTAL frequency/2) is then directly output on P56 (Figure 27).
Internal clock
OSC
+2
P56
TOUT
TMR TMR Figure 27. Internal Clock Output Using TOUT
While programmed as TOUT, P56 cannot be modified by a write to port register P5. However, the Z8 software can examine P56's current output by reading the port register. TIN Modes The Timer Mode register TMR (F1h) (Figure 28) is used in conjunction with the Prescaler register PRE1 (F3h) (Figure 29) to configure P52 as TIN. TIN is used in conjunction with T1 in one of four modes:
* * * *
External clock input Gated internal clock Triggered internal clock Retriggerable internal clock
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R241 TMR Timer Mode Register (F1h; Read/Write)
D5 D4
TIN modes External clock input = 00 Gate input = 01 Trigger input = 10 (non-retriggerable) Trigger input = 11 (retriggerable) Figure 28. Timer Mode Register TIN Operation
R243 PRE1 Prescaler 1 Register (F3h; Write Only)
D1
Clock source 1 = T1 internal 0 = T1 external (TIN) Figure 29. Prescaler 1 TIN Operation
The T1 counter/timer clock source must be configured for external by setting PRE1 bit D2 to 0. The Timer Mode register bits D5 and D4 can then be used to select the TIN operation. For T1 to start counting as a result of a TIN input, the Enable Count bit D3 in TMR must be set to 1. When using TIN as an external clock or a gate input, the initial values must be loaded into the down-counters by setting the Load bit D2 in TMR to 1 before counting begins. Initial values are automatically loaded in Trigger and Retrigger modes, so software loading is unnecessary. Configure P52 as an input line by setting P5M bit D2 to 1.
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Each High-to-Low transition on TIN generates interrupt request IRQ0, regardless of the selected TIN mode or the enabled/disabled state of T1. IRQ0 must therefore be masked or enabled according to the needs of the application. External Clock Input Mode The TIN External Clock Input mode (TMR bits D5 and D4 both set to 0) supports the counting of external events, where an event is considered to be a High-to-Low transition on TIN (see Figure 30) occurrence (single-pass mode) or on every nth occurrence (continuous mode) of that event.
TMR D5-D4 = 00 TIN clock P52 D D PRE1 T1 IRQ5
Internal clock Figure 30. External Clock Input Mode
IRQ0
Gated Internal Clock Mode The TIN Gated Internal Clock mode (TMR bits D5 and D4 set to 0 and 1, respectively) measures the duration of an external event. In this mode, the T1 prescaler is driven by the internal timer clock, gated by a High level on TIN (see Figure 31). T1 counts while TIN is High and stops counting when TIN is Low. Interrupt request IRQ0 is generated on the High-to-Low transition of TIN, signaling the end of the gate input. Interrupt request IRQ5 is generated if T1 reaches its end-of-count.
OSC
+2 TMR D5-D4 = 01
Internal clock
+4
PRE1
T1
IRQ5
TIN gate
P52
D
D
IRQ0
Figure 31. Gated Clock Input Mode
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Triggered Input Mode The TIN Triggered Input mode (TMR bits D5 and D4 set to 1 and 0, respectively) causes T1 to start counting as the result of an external event (see Figure 32). T1 is then loaded and clocked by the internal timer clock following the first High-to-Low transition on the TIN input. Subsequent TIN transitions do not affect T1. In the single-pass mode, the Enable bit is reset whenever T1 reaches its end-of-count. Further TIN transitions have no effect on T1 until software sets the Enable Count bit again. In continuous mode, when T1 is triggered, counting continues until software resets the Enable Count bit. Interrupt request IRQ5 is generated when T1 reaches its end-of-count.
OSC +2
Internal clock TMR D5 = 1 +4 Edge trigger PRE1 T1 IRQ5
TIN trigger
P52
D
D
TMR D5-D4 = 11
IRQ0 Figure 32. Triggered Clock Mode
Retriggerable Input Mode The TIN Retriggerable Input mode (TMR bits D5 and D4 both set to 1) causes T1 to load and start counting on every occurrence of a High-to-Low transition on TIN (see Figure 32). Interrupt request IRQ5 is generated if the programmed time interval (determined by T1 prescaler and counter/timer register initial values) has elapsed since the last High-to-Low transition on TIN. In single-pass mode, the end-of-count resets the Enable Count bit. Subsequent TIN transitions do not cause T1 to load and start counting until software sets the Enable Count bit again. In continuous mode, counting continues when T1 is triggered until software resets the Enable Count bit. When enabled, each High-to-Low TIN transition causes T1 to
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reload and restart counting. Interrupt request IRQ5 is generated on every end-ofcount. T8 and T16 Timer Operation The T8 timer is a programmable 8-bit counter/timer with two 8-bit capture registers and two 8-bit load registers. The T16 timer is a programmable 16-bit counter/ timer with one 16-bit capture register pair and one 16-bit load register pair. See Figure 33. The T8 and T16 counters/timers have two modes of operation:
*
The transmit mode is used to generate complex waveforms. There are two submodes: - The normal mode can be used in single-pass or modulo-N (repeating) mode. - The ping-pong mode is used when the T8 timer counts down, enables the T16 timer that counts down, enabling T8, and so on, until the mode is disabled. The demodulation mode is used to capture and demodulate complex waveforms.
*
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HI16 8
LO16 8
16-Bit T16 Input 16 Glitch Filter SCLK
Timer 16 1248
Clock Divider
8 TC16H HI8
8
TC16L LO8
T16 Clocked
And/Or Logic
Timer 8/16
Edge Detect Circuit
8 8-Bit T8 8 TC8H
8 Timer 8 1248 8 TC8L SCLK Clock Divider T8 Clock Divider
Figure 33. Counter/Timer Architecture
T8 Transmit Mode Before T8 is enabled, the output of T8 depends on CTR1, D1. If CTR1, D1 is 0, T8_OUT is 1. If CTR1, D1 is 1, T8_OUT is 0. When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If the initial value (CTR1 D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into the counter. In single-pass mode (CTR0 D6), T8 counts down to 0 and stops, T8_OUT toggles, the time-out status bit (CTR0 D5) is set, and a time-out interrupt can be generated if it is enabled (CTR0 D1). In modulo-N mode, upon reaching terminal count, T8_OUT is toggled, but no interrupt is generated. Then T8 loads a new count (if T8_OUT level is 0), TC8L is loaded; if T8_OUT is 1, TC8H is loaded.
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T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5), and generates an interrupt if enabled (CTR0 D1). This completes one cycle. T8 then loads from TC8H or TC8L, according to the T8_OUT level, and repeats the cycle. The user can modify the values in TC8H or TC8L at any time.The new values take effect when they are loaded. Do not write these registers at the time the values are to be loaded into the counter/timer. An initial count of 1 is not allowed. An initial count of 0 causes TC8 to count from 0 to FFh to FEh. Transition from 0 to FFh is not a time-out condition (see Figure 34).
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T8 (8-Bit) Transmit Mode
No
T8_Enable Bit Set CTR0 D7 Yes
Reset T8_Enable Bit 0 Load TC8L Reset T8_OUT
CTR1 D1 Value
1 Load TC8H Set T8_OUT
Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int. if Enabled
Enable T8
No
T8_Timeout Yes
Single Pass
Single Pass? Modulo-N 1 T8_OUT Value 0 Load TC8H Set T8_OUT
Load TC8L Reset T8_OUT
Enable T8
Set Time-out Status Bit (CTR0 D5) and Generate Timeout_Int. if Enabled
No
T8_Timeout Yes Disable T8
Figure 34. Transmit Mode Flowchart
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Note: Do not use the same instructions for stopping the counter/ timers and setting the status bits. Two successive commands are necessary--the first command for stopping counter/timers and the second command for resetting the status bits-- because one counter/timer clock interval must complete for the initiated event to actually occur. T8 Demodulation Mode Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising, falling, or both, depending on CTR1 D5, D4) is detected, it starts to count down. When a subsequent edge (rising, falling, or both, depending on CTR1 D5, D4) is detected during counting, the current value of T8 is one's complemented and put into one of the capture registers. If T8 is a positive edge, data is placed in LO8. If T8 is a negative edge, data is placed in H18. One of the edge-detect status bits (CTR1 D1, D0) is set, and an interrupt can be generated if enabled (CTR0 D2). Meanwhile, T8 is loaded with TC8H and starts counting again. If T8 reaches 0, the time-out status bit (CTR0 D5) is set, and an interrupt can be generated if enabled (CTR0 D1), and T8 continues counting from FFh (see Figure 35).
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T8 (8-Bit) Demodulation Mode
No
T8 Enable CTR0, D7 Yes
FFh TC8
No
First Edge Present Yes
Disable TC8
Enable TC8
No
T8_Enable Bit Set Yes No Edge Present Yes Set Edge Present Status Bit and Trigger Data Capture Int. if Enabled T8 Time Out Yes Set Time-out Status Bit and Trigger Time Out Int. if Enabled No
Continue Counting
Figure 35. Demodulation Mode Flowchart
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T16 Transit Mode In normal or ping-pong mode, the output of T16, when not enabled, is dependent on CTR1, D0. If CTR1, D0 is a 0, T16_OUT is a 1; if CTR1, D0 is a 1, T16_OUT is 0. The user can force the output of T16 to either a 0 or 1, whether it is enabled or not, by programming CTR1 D3, D2 to a 10 or 11. When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched to its initial value (CTR1 d0). When T16 counts down to 0, T16_OUT is toggled (in normal or ping-pong mode), an interrupt is generated if enabled (CTR2 D1), and a status bit (CTR2 D5) is set. If it is in modulo-N mode, it is loaded with TC16H * 256 + TC16L, and the counting continues. The user can modify the values in TC16H and TC16L at any time. The new values take effect when they are loaded. Do not load these registers at the time the values are to be loaded into the counter/timer. An initial count of 1 is not allowed. An initial count of 0 causes T16 to count from 0 to FFFFh to FFFEh. Transition from 0 to FFFFh is not a time-out condition. T16 Demodulation Mode Program TC16L and TC16H to FFh. After T16 is enabled, when the first edge (rising, falling, or both, depending on CTR1 D5, D4) is detected, T16 captures HI16 and LO16, reloads, and begins counting. Ping-Pong Mode This operation mode is only valid in transmit mode. T8 and T16 must be programmed in single-pass mode (CTR0 D6, CTR2 D6), and ping-pong mode must be programmed in CTR1 D3, D2. The user can begin the operation by enabling either T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT is set to this initial value (CTR1 D1). According to T8_OUT's level, TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it stops. T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the pingpong operation, write 00 to bits D3 and D2 or CTR1. Note: Enabling ping-pong operation while the counters/timers are running can cause intermittent counter/timer function. Disable the counters/timers, then reset the status flags before starting the ping-pong mode.
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Control and Status Registers
The Z86D99/Z86L99 family has 4 I/O port registers, 33 status and control registers, and 233 general-purpose RAM registers. The I/O port and control registers are included in the general-purpose register memory to allow any Z8 instruction to process I/O or control information directly, thus eliminating the requirement for special I/O or control instructions. The Z8 instruction set permits direct access to any of these 37 registers. In addition, each of the 233 general-purpose registers can also function as an accumulator, an address pointer, or an index register. Registers identified as "Reserved" do not exist or have not been implemented in this design.
Register Summary
Table 10 through Table 13 summarize the name and location of all registers. The register-by-register descriptions follow this section.
Table 10. I/O Port Registers (Group 0, Bank 0, Registers 0-F) Grp/Bnk Reg (00h) rF (00h) rE (00h) rD (00h) rC (00h) rB (00h) rA (00h) r9 (00h) r8 (00h) r7 (00h) r6 (00h) r5 (00h) r4 (00h) r3 (00h) r2 (00h) r1 (00h) r0 Register Function General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register General-Purpose RAM Register Analog/Digital Converted Data Port 6 Control Register Port 5 Control Register Port 4 Control Register Reserved Port 2 Control Register Reserved Reserved Identifier GPR GPR GPR GPR GPR GPR GPR GPR ADCDATA P6 P5 P4 P2
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Table 11. Control and Status Registers (Group F, Bank 0, Registers 0-F) Grp/Bnk Reg (F0h) rF (F0h) rE (F0h) rD (F0h) rC (F0h) rB (F0h) rA (F0h) r9 (F0h) r8 (F0h) r7 (F0h) r6 (F0h) r5 (F0h) r4 (F0h) r3 (F0h) r2 (F0h) r1 (F0h) r0 Register Function Stack Pointer General-purpose RAM Register Register Pointer Program Control Flag Register Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Reserved Port 3 Mode Register Port 2 Mode Register Reserved Reserved T1 Prescale Register T1 Data Register T1 Mode Register Reserved Identifier SP GPR RP Flags IMR IRQ IPR P3M P2M
PRE1 T1 TMR
Table 12. Timer Control Registers (Group 0, Bank D, Registers 0-F) Grp/Bnk Reg (0Dh) rF (0Dh) rE (0Dh) rD (0Dh) rC (0Dh) rB (0Dh) rA (0Dh) r9 (0Dh) r8 (0Dh) r7 (0Dh) r6 (0Dh) r5 (0Dh) r4 (0Dh) r3 (0Dh) r2 (0Dh) r1 (0Dh) r0 Register Function Reserved Reserved Reserved Low-Battery Detect Flag T16 MS-Byte Capture Register T16 LS-Byte Capture Register T8 High Capture Register T8 Low Capture Register T16 MS-Byte Hold Register T16 LS-Byte Hold Register T8 High Hold Register T8 Low Hold Register T8/T16 Control Register B T16 Control Register T8/T16 Control Register A T8 Control Register Identifier
LB HI8 LO8 HI16 LO16 TC16H TC16L TC8H TC8L CTR3 CTR2 CTR1 CTR0
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Table 13. SMR and Port Mode Registers (Group 0, Bank F, Registers 0-F) Grp/Bnk Reg (0Fh) rF (0Fh) rE (0Fh) rD (0Fh) rC (0Fh) rB (0Fh) rA (0Fh) r9 (0Fh) r8 (0Fh) r7 (0Fh) r6 (0Fh) r5 (0Fh) r4 (0Fh) r3 (0Fh) r2 (0Fh) r1 (0Fh) r0 Register Function Reserved Reserved Reserved Reserved Stop Mode Recovery Register Reserved Reserved ADC Control Register Reserved Port 6 Mode Port 5 Stop Mode Recovery Port 5 Mode Register Reserved Port 4 Mode Register Port 2 Stop Mode Recovery Port Configuration Register Identifier
SMR
ADCCTRL P6M P5SMR P5M P4M P2SMR P456CON
Register Error Conditions
Registers in the Z8 Standard Register File must be used correctly because certain conditions produce inconsistent results and must be avoided.
* *
Registers F5h-F9h are write-only registers. If an attempt is made to read these registers, FFh is returned. Reading any write-only register returns FFh. When the Register Pointer (register FDH) is read, the least significant four bits (lower nibble) indicate the current Expanded Register File Bank. (For example, 0000 indicates the Standard Register File, while 1010 indicates Expanded Register File Bank A.) Writing to bits that are selected as timer outputs changes the I/O register but has no effect on the pin signal. The Z8 instruction DJNZ uses any general-purpose working register as a counter. Logical instructions such as OR and AND require that the current contents of the operand be read. They do not function properly on write-only registers.
* * *
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Registers (Grouped by Function)
The following is a summary of the 37 special-purpose registers of the Z86D99/ Z86L99 family grouped by function. The following are the functional groups:
* * * * * * *
Flags and Pointers Analog-to-Digital Converter Control Interrupt Control I/O Port Control Timer Control--General-Purpose Timer (T1) Timer Control--T8 and T16 Timers Stop-Mode Recovery Control
For any of the registers described in this section (see Table 14), bits identified as "Reserved" either do not exist (meaning they have not been implemented in this design) or have a special purpose in a ZiLOG engineering or test environment. Caution: Do not attempt to use these bits as the results are unpredictable and meaningless.
Table 14. Register Description Locations Address Grp/Bnk Register
00h 00h 00h 00h 00h 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh 0Dh
Register Function Port 2 Data Port 4 Data Port 5 Data Port 6 Data ADC Data T8 Timer Control T8/T16 Control (A) T16 Timer Control T8/T16 Control (B) T8 Low Load T8 High Load T16 Low Load T16 High Load T16 Low Capture T16 High Capture T8 Low Capture
Symbol P2 P4 P5 P6 ADCDATA CTR0 CTR1 CTR2 CTR3 TC8L
Location page 68 page 69 page 70 page 71 page 62 page 77 page 74 page 80 page 76 page 79 page 79 page 82 page 82 page 81 page 81 page 78
r2 (R2) r4 (R4) r5 (R5) r6 (R6) r7 (R7) r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10
TC8H TC16L LO16 LO8

TC16H HI16
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Table 14. Register Description Locations (Continued) Address Grp/Bnk Register
0Dh 0Dh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh F0h F0h F0h F0h F0h F0h F0h F0h F0h F0h F0h
Register Function T8 High Capture Low Battery Detect Port Configuration (A) Port 2 SMR Source Port 4 Mode Port 5 Mode Port 5 SMR Source Port 6 Mode ADC Control Stop Mode Recovery T1 Timer Mode T1 Timer Data T1 Timer Prescale Port 2 Mode Port Configuration (B) Interrupt Priority Interrupt Request Interrupt Mask Program Control Flags Register Pointer Stack Pointer
Symbol HI8 LB P456CON P2SMR P4M P5M P5SMR P6M ADCCTRL SMR TMR T1 PRE1 P2M P3M IPR IRQ IMR Flags RP SP
Location page 78 page 60 page 67 page 84 page 69 page 70 page 84 page 71 page 61 page 83 page 72 page 72 page 73 page 68 page 67 page 64 page 65 page 63 page 57 page 58 page 59
r11 r12 r0 r1 r2 r4 r5 r6 r8 r11 r1 (R241) r2 (R242) r3 (R243) r6 (R246) r7 (R247) r9 (R249) r10 (R250) r11 (R251) r12 (R252) r13 (R253) r15 (R255)
This
Note:
register is not reset following Stop Mode Recovery (SMR).
Flags and Pointer Registers In addition to the three standard Z8 flag and pointer registers (Program Control Register Pointer, and Stack Pointer), the Z86D99/Z86L99 family includes a LowBattery Detect Flag register.
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Program Control Flag Register (Flags) The Program Control Flag register (see Table 15) reflects the current status of the Z8 as shown in Table 15. The FLAGS register contains six bits of status information that are set or cleared by CPU operations. Four of the bits (C, V, Z, and S) can be tested for use with conditional jump instructions. Two flags (H and D) cannot be tested and are used for BCD arithmetic. The two remaining flags in the register (F1 and F2) are available to the user, but they must be set or cleared by instructions and are not usable with conditional jumps.
Table 15. FLAGS Register [Group/Bank F0h, Register C (R252)] Bit Bit/Field R/W Reset Bit Position 7_______ 7 C R/W X 6 Z R/W X 5 S R/W X 4 V R/W X 3 D R/W X 2 H R/W X 1 F2 R/W X 0 F1 R/W X
R = Read, W = Write, X = Indeterminate Bit/Field Carry Flag (C) R/W R/W Value 1 Description Indicates the "carry out" of bit 7 position of a register being used as an accumulator; on Rotate and Shift instructions this bit contains the most recent value shifted out of the specified register Indicates that the contents of an accumulator register is zero following an arithmetic or logical operation Stores the value of the most significant bit of a result following an arithmetic, logical, Rotate, or Shift operation; in arithmetic operations on signed numbers, a positive number is identified by a 0, and a negative number is identified by a 1 For signed arithmetic, Rotate, and Shift operations, the flag is set to 1 when the result is greater than the maximum possible number (>127) or less than the minimum possible number (<-128) that can be represented in two's complement form; following logical operations, this flag is set to 0
_6______
Zero Flag (Z)
R/W
1
__5_____
Sign Flag (S)
R/W
X
___4____
Overflow Flag (V)
R/W
1
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Table 15. FLAGS Register [Group/Bank F0h, Register C (R252)] (Continued) ____3___ Decimal Adjust Flag (D) Half Carry Flag (H) R/W 1 0 1 0 Used for BCD arithmetic--after a subtraction, the flag is set to 1; following an addition, it is cleared to 0 Set to 1, whenever an addition generates a "carry out" of bit position 3 (overflow) of an accumulator; or subtraction generates a "borrow into" bit 3 User definable User definable
_____2__
R/W
______1_ _______0
User Flag (F2) User Flag (F1)
R/W R/W
1 0 1 0
Register Pointer (RP) Z8 instructions can access registers directly or indirectly using either a 4-bit or 8bit address field. The upper nibble of the Register Pointer, as described in Table 16, contains the base address of the active Working Register GROUP. The lower nibble contains the base address of the Expanded Register File BANK. When using 4-bit addressing, the 4-bit address of the working register (r0 to rF) is combined with the upper nibble of the Register Pointer (identifying the WR GROUP), thus forming the 8-bit actual address.
Table 16. RP Register [Group/Bank F0h, Register D (R253)] Bit Bit/Field R/W Reset Bit Position 7654_____ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
Working Register Group
Expanded Register File Bank
R = Read, W = Write, X = Indeterminate Bit/Field R/W Value X Description Identifies 1 of 16 possible WR Groups, each containing 16 Working Registers Identifies 1 of 16 possible ERF Banks; only Banks 0, D, and F are valid for the Z86D99/Z86L99 family
Working Register R/W Group Pointer Expanded Register File Bank Pointer R/W
_____3210
X
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Stack Pointer (SP) The Z86D99/Z86L99 family of products is configured for an internal stack. The size of the stack is limited only by the available memory space or general-purpose RAM registers dedicated to this task. An 8-bit stack pointer, as described in Table 17, is used for all stack operations.
Table 17. SP Register [Group/Bank F0h, Register F (R255)] Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W X 6 R/W X 5 R/W X 4 R/W X 3 R/W X 2 R/W X 1 R/W X 0 R/W X
Stack Pointer
R = Read, W = Write, X = Indeterminate Bit/Field Stack Pointer R/W R/W Value X Description Points to the data stored on the top of the stack; an overflow or underflow can occur if the stack address is incremented or decremented during normal stack operations
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Low-Battery Detect Flag (LB) When the Z86D99/Z86L99 is used in a battery-operated application, one of the on-chip comparators can be used to check that the VCC is at the required level for correct operation of the device. When voltage begins to approach the VBO point, an on-chip low-battery detection circuit is tripped, which in turn sets a user-readable flag. The LB register, as described in Table 18, is used to set and reset the LB flag.
Table 18. LB Register (Group/Bank 0Dh, Register C) Bit Bit/Field R/W Reset Bit Position 76543___ _____2__ 7 6 5 4 3 2 Pad LVD W 1 W 1 W 1 R/W X 1 LVD_ Flag R/W 0 0 LVD_ Enable R/W 0
Reserved W 1 W 1
R = Read, W = Write, X = Indeterminate Bit/Field Reserved Pad LVD R/W R W R R W ______1_ LVD_Flag R R W R/W Value 1 X 1 0 X 1 0 X 1 0 Description Always reads 11111 No Effect Pad is not regulated when P43=0 (VpadVmin; see page 33) Reset Pad LB flag LB Flag Set if VDD_______0
LVD_Enable
Note: * When LVD is enabled, IRQ5 is set only for low-voltage detection. Timer 1 will not generate an interrupt request.
Note: The LB flag will be valid after enabling the detection for 20 S (design estimation, not tested in production). LB does not work at STOP mode. It must be disabled during STOP mode in order to reduce current.
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Analog-to-Digital Converter Control Registers The Z86D99/Z86L99 family features an 8-bit analog-to-digital converter with external voltage references. The output of the ADC is stored in the ADC Data Register, as shown in Table 20. The ADC is configured using the ADC Control Register, as shown in Table 19.
Table 19. ADCCTRL Register (Group/Bank 0Fh, Register 8) Bit 7 P47_ A/D R/W 0 6 P46_ A/D R/W 0 5 P45_ A/D R/W 0 4 P44_ A/D R/W 0 3 2 1 0
Bit/Field R/W Reset Bit Position 7_______ _6______ __5_____ ___4____ ____32__
Channel Selection R/W 0 R/W 0
ADC A/D Pwr Clock On Select R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field P47_A/D P46_A/D P45_A/D P44_A/D Channel Selection R/W R/W R/W R/W R/W R/W Value 1 0 1 0 1 0 1 0 11 10 01 00 1 0 1 0 Description P47 configured as A/D Input P47 configured as digital input P46 configured as A/D Input P46 configured as digital input P45 configured as A/D Input P45 configured as digital input P44 configured as A/D Input P44 configured as digital input Channel 3 (P47) Channel 2 (P46) Channel 1 (P45) Channel 0 (P44) ON OFF SCLK/2 SCLK
______1_ _______0
A/D_PowerON
R/W
ADC Clock Select R/W
ADC Control Register (ADCCTRL) The ADCCTRL register controls the operation of the analog-to-digital converter. Bits 2 and 3 of the ADCCTRL register determine which of the four analog input channels feeds into the ADC at any given time. Bits 4 through 7 enable or disable the digital input buffer. When configured as an ADC input channel, the port has to be configured in Input Mode and with the digital input buffer disabled.
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ADC Data Register (ADCDATA) The ADCDATA register is a read-only register that contains the digital output of the analog-to-digital converter. See Table 20.
)
Table 20. ADCDATA Register (Group/Bank 00h, Register 7) Bit Bit/Field R/W Reset Bit Position 76543210 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0
ADC Data
R = Read, W = Write, X = Indeterminate Bit/Field ADC Data R/W R W Value Data X Description Output of the ADC No Effect
Interrupt Control Registers The Z8 allows up to six different interrupts from a variety of sources. These interrupts can be masked and their priorities set by using the Interrupt Mask Register and Interrupt Priority Register. The Interrupt Request Register stores the interrupt requests for both vectored and polled interrupts.
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Interrupt Mask Register The IMR, as described in Table 21, individually or globally enables the six interrupt requests. Bit 7 of the IMR is the master enable and must be set before any of the individual interrupt requests can be recognized. Bit 7 must be set and reset by the enable interrupts and disable interrupts instructions only. The IMR is automatically reset during an interrupt service routine and set following the execution of an Interrupt Return (IRET) instruction.
Table 21. IMR (Group/Bank 0Fh, Register B) Bit Bit/Field R/W Reset Bit Position 7_______ _6______ __5_____ ___4____ ____3___ _____2__ ______1_ _______0 7 6 5 4 IRQ4 R/W 0 3 IRQ3 R/W 0 2 IRQ2 R/W 0 1 IRQ1 R/W 0 0 IRQ0 R/W 0
ReMaster served IRQ5 R/W 0 R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field Master Reserved IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 R/W R/W R W R/W R/W R/W R/W R/W R/W Value 1 0 1 X 1 0 1 0 1 0 1 0 1 0 1 0 Description Enable Master Interrupt Disable Master Interrupt Always reads 1 No Effect Enable IRQ5 Disable IRQ5 Enable IRQ4 Disable IRQ4 Enable IRQ3 Disable IRQ3 Enable IRQ2 Disable IRQ2 Enable IRQ1 Disable IRQ1 Enable IRQ0 Disable IRQ0
Note: Bit 7 must be reset by the DI instruction before the contents of the Interrupt Mask Register or the Interrupt Priority Register are changed except in the following situations: - - Immediately after a hardware reset Immediately after executing an interrupt service routine and before IMR bit 7 has been set by any instruction
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Interrupt Priority Register (IPR) The IPR, as described in Table 22, is a write-only register that sets priorities for the vectored interrupts in order to resolve simultaneous interrupt requests. There are 48 sequence possibilities for interrupts. The six interrupts, IRQ0 to IRQ5, are divided into three groups of two interrupt requests each, as follows:
* * *
)
Group A consists of IRQ3 and IRQ5 Group B consists of IRQ0 and IRQ2 Group C consists of IRQ1 and IRQ4
Table 22. IPR (Group/Bank 0Fh, Register 9) Bit Bit/Field R/W Reset Bit Position 76______ __5_____ ___43__0 7 6 5 4 3 2 1 0
Reserved W 0 W 0
Grp A IRQ3_5 Int_Group W 0 W 0 W 0
Grp B Grp C Int_ IRQ0_2 IRQ1_4 Group W 0 W 0 W 0
R = Read, W = Write, X = Indeterminate Bit/Field Reserved Grp A Priority: IRQ3 and IRQ5 Interrupt Group Priority R/W W W W Value X 1 0 111 110 101 100 011 010 001 000 1 0 1 0 Description No Effect IRQ3>IRQ5 (Group A) IRQ5>IRQ3 Reserved B>A>C C>B>A B>C>A A>C>B A>B>C C>A>B Reserved IRQ0>IRQ2 (Group B) IRQ2>IRQ0 IRQ4>IRQ1 (Group C) IRQ1>IRQ4
_____2__ ______1_
Grp B Priority: IRQ0 and IRQ2 Grp C Priority: IRQ1 and IRQ4
W W
Priorities can be set both within and between groups using the IPR. Bits 1, 2, and 5 of the IPR define the priority of individual members within the groups. Bits 0, 3, and 4 are encoded to define six priority orders between the three groups. Bits 6 and 7 are reserved.
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Interrupt Request Register The IRQ, as described in Table 23, is a read/write register that stores the interrupt requests for both vectored and polled interrupts. When an interrupt request is made by any of the six interrupts, the corresponding bit in the IRQ is set to 1.
Table 23. IRQ (Group/Bank 0Fh, Register A) Bit Bit/Field R/W Reset Bit Position 76______ 7 6 5 Set IRQ5 R/W 0 4 Set IRQ4 R/W 0 3 Set IRQ3 R/W 0 2 Set IRQ2 R/W 0 1 Set IRQ1 R/W 0 0 Set IRQ0 R/W 0
Interrupt Edge R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field Interrupt Edge Trigger R/W R/W Value 11 10 01 00 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Description P51 Rise/FallingP52 Rise/Falling P51 Rising P52 Falling P51 FallingP52 Rising P51 FallingP52 Falling IRQ5 Inactive IRQ5 Active Set IRQ5 Reset IRQ5 IRQ4 Inactive IRQ4 Active Set IRQ4 Reset IRQ4 IRQ3 Inactive IRQ3 Active Set IRQ3 Reset IRQ3 IRQ2 Inactive IRQ2 Active Set IRQ2 Reset IRQ2 IRQ1 Inactive IRQ1 Active Set IRQ1 Reset IRQ1 IRQ0 Inactive IRQ0 Active Set IRQ0 Reset IRQ0
__5_____
Set IRQ5
R R W W R R W W R R W W R R W W R R W W R R W W
___4____
Set IRQ4
____3___
Set IRQ3
_____2__
Set IRQ2
______1_
Set IRQ1
_______0
Set IRQ0
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Whenever a power-on reset is executed, the IRQ is reset to 00h and disabled. Before the IRQ accepts requests, it must be enabled by executing an enable interrupts instruction. Note: IRQ is always cleared to 00h and is in read-only mode until the first EI instruction that enables the IRQ to be read/write. Setting the Global Interrupt Enable bit in the Interrupt Mask Register (IMR bit 7) does not enable the IRQ. Execution of an EI instruction is required. For polled processing, IRQ must be initialized by an EI instruction. To properly initialize the IRQ, the following code is provided:
CLR EI IMR ; ; ; ; ; make sure vectored interrupts are disabled enable IRQ, otherwise it is read only not necessary, if interrupts were previously enabled disable interrupt handling
DI
IMR is cleared before the IRQ enabling sequence to ensure no unexpected interrupts occur when EI is executed. This code sequence must be executed before programming the application required values for IPR and IMR. I/O Port Control Registers Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output register, and an associated buffer and control logic. Because there are separate input and output registers associated with each port, writing bits defined as inputs stores the data in the output register. This data cannot be read as long as the bits are defined as inputs. However, if the bits are reconfigured as output, the data stored in the output register is reflected on the output pins and can then be read. This mechanism allows the user to initialize the outputs before driving their loads.
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Port Configuration Registers (P456CON and P3M) The port configuration register (described in Table 24) switches the comparator inputs from digital to analog and allows Ports 4, 5, and/or 6 to be switched from push/pull active outputs to open drain outputs. In ZiLOG Test Mode, bit 3 of this register is used to enable the Address Strobe/Data Strobe. Bit 3 is not available in User Mode.
Table 24. P456CON Register (Group/Bank 0Fh, Register 0) Bit Bit/Field R/W Reset Bit Position 76______ 7 6 5 4 3 2 1 P5_ Output W 1 0 P4_ Output W 1
Not Used R/W 0 R/W 0
P51_ P52_ Mode Mode R/W 0 R/W 0
P6_ Reserved Output R/W 0 W 1
R = Read, W = Write, X = Indeterminate Bit/Field Not Used R/W R/W Value Description These bits exist but do not have any function assigned to them; they are reserved for future extensions and must not be used. 1 0 1 0 Analog (P50, P51 as Inputs) Digital inputs Analog comparator inputs (P52, P53 configured as Inputs) Digital inputs Push-Pull Active Open Drain Outputs Always reads back 1* Push-Pull Active Open Drain Outputs Always reads back 1* Push-Pull Active Open Drain Outputs Always reads back 1*
__5_____ ___4____
Comparator 1 Mode Comparator 2 Mode Reserved Port 6 Output Configuration Port 5 Output Configuration Port 4 Output Configuration
R/W R/W
____3___ _____2__
W
1 0 1 0 1 0
______1_
W
_______0
W
Note: *Do not use the read-modify-write instructions (for example, OR and AND) with this register. Bits 0, 1, and 2 always read back 1. Note: For Z86L990/L991, P43 can never be configured as push-pull. After any reset, P43 is configured as tristate high impedance.
Port 2 outputs are configured using the P3M Register, shown in Table 25. Bit 0 of the P3M Register switches Port 2 from push/pull active to open drain outputs. No other bits in this register are implemented.
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Table 25. P3M Register [Group/Bank F0h, Register 7 (R247)] Bit Bit/Field R/W Reset Bit Position 7654321_ 7 6 5 4 3 2 1 0 P2_ Output W 1 W 1 W 1 W 1 W 1 W 1
Reserved W 1 W 1
R = Read, W = Write, X = Indeterminate Bit/Field Reserved R/W R W W Value 1 X 1 0 Description Always reads 1111111 No Effect Push-Pull Active Open Drain Outputs
_________0 Port 2 Output Configuration
Port 2 Control and Mode Registers (P2 and P2M) Port 2 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 26. Each of the eight Port 2 I/O lines can be independently programmed as either input or output using the Port 2 Mode Register (see Table 27.)
Table 26. P2 Register [Group/Bank 00h, Register 2 (R2)] Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W X 6 R/W X 5 R/W X 4 R/W X 3 R/W X 2 R/W X 1 R/W X 0 R/W X
Port 2 Data
R = Read, W = Write, X = Indeterminate Bit/Field Port 2 Data R/W R/W Value Data Description Port 2 Input/Output Register
Table 27. P2M Register [Group/Bank F0h, Register 6 (R246)] Bit Bit/Field R/W Reset Bit Position 76543210 (by bit) 7 P27M W 1 6 P26M W 1 5 P25M W 1 4 P24M W 1 3 P23M W 1 2 P22M W 1 1 P21M W 1 0 P20M W 1
R = Read, W = Write, X = Indeterminate Bit/Field Port 2 Mode Select R/W R W W Value 1 1 0 Description Always reads 11111111 Input Output
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A bit set to 1 in the P2M Register configures the corresponding bit in Port 2 as an input, while a bit set to 0 configures an output line. Port 4 Control and Mode Registers (P4 and P4M) Port 4 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 28. Each of the eight Port 4 I/O lines can be independently programmed as either input or output using the Port 4 Mode Register (see Table 29.)
Table 28. P4 Register [Group/Bank 00h, Register 4 (R4)] Bit Bit/Field R/W Reset Bit Position 76543210
.
7 R/W X
6 R/W X
5 R/W X
4 R/W X
3 R/W X
2 R/W X
1 R/W X
0 R/W X
Port 4 Data
R = Read, W = Write, X = Indeterminate Bit/Field Port 4 Data R/W R/W Value Data Description Port 4 Input/Output Register
Table 29. P4M Register (Group/Bank 0Fh, Register 2) Bit Bit/Field R/W Reset Bit Position 7654_210 (by bit) ____3___ 7 P47M R/W 1 6 P46M R/W 1 5 P45M R/W 1 4 P44M R/W 1 3 P43M R/W 1 2 P42M R/W 1 1 P41M R/W 1 0 P40M R/W 1
R = Read, W = Write, X = Indeterminate Bit/Field Port 4 Mode Select P43 Mode Select R/W R/W R/W Value 1 0 0 1 Description Input Output Output Tristate High Impedance (available on Z86L990/L991 only)
A bit set to 1 in the P4M Register configures the corresponding bit in Port 4 as an input, while a bit set to 0 configures an output line. Note: P43, the controlled current output pad, cannot be configured as an input. (P43 read = P43 out)
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Port 5 Control and Mode Registers (P5 and P5M) Port 5 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 30. Each of the eight Port 5 I/O lines can be independently programmed as either input or output using the Port 5 Mode Register (see Table 31.)
Table 30. P5 Register [Group/Bank 00h, Register 5 (R5)] Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W X 6 R/W X 5 R/W X 4 R/W X 3 R/W X 2 R/W X 1 R/W X 0 R/W X
Port 5 Data
R = Read, W = Write, X = Indeterminate Bit/Field Port 5 Data R/W R/W Value Data Description Port 5 Input/Output Register
Table 31. P5M Register (Group/Bank 0Fh, Register 4) Bit Bit/Field R/W Reset Bit Position 7654__10 (by bit) ____32__ 7 P57M R/W 1 6 P56M R/W 1 5 P55M R/W 1 4 P54M R/W 1 3 P53M R/W 1 2 P52M R/W 1 1 P51M R/W 1 0 P50M R/W 1
R = Read, W = Write, X = Indeterminate Bit/Field Port 5 Mode Select P53, P52 Mode Select R/W R/W R/W Value 1 0 1 Description Input Output Input Regardless of what is written to this pin, P53 and P52 are always in input mode.
A bit set to a 1 in the P5M Register configures the corresponding bit in Port 5 as an input, while a bit set to 0 configures an output line. Note: Regardless of how P5M bits 2 and 3 are set, P52 and P53 are always in input mode.
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Port 6 Control and Mode Registers (P6 and P6M) Port 6 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 32. Each of the eight Port 6 I/O lines can be independently programmed as either input or output using the Port 6 Mode Register (see Table 33.)
Table 32. P6 Register [Group/Bank 00h, Register 6 (R6)] Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W X 6 R/W X 5 R/W X 4 R/W X 3 R/W X 2 R/W X 1 R/W X 0 R/W X
Port 6 Data
R = Read, W = Write, X = Indeterminate Bit/Field Port 6 Data R/W R/W Value Data Description Port 6 Input/Output Register
Table 33. P6M Register (Group/Bank 0Fh, Register 6) Bit Bit/Field R/W Reset Bit Position 76543210 (by bit) 7 P67M R/W 1 6 P66M R/W 1 5 P65M R/W 1 4 P64M R/W 1 3 P63M R/W 1 2 P62M R/W 1 1 P61M R/W 1 0 P60M R/W 1
R = Read, W = Write, X = Indeterminate Bit/Field Port 6 Mode Select R/W R/W Value 1 0 Description Input Output
A bit set to 1 in the P6M Register configures the corresponding bit in Port 6 as an input, while a bit set to 0 configures an output line. Timer Control Registers--General-Purpose Timer (T1) The Z86D99/Z86L99 family provides one standard 8-bit Z8 counter/timer, T1, driven by its own 6-bit prescaler, PRE1. T1 is independent of the processor instruction sequence, relieving software from time-critical operations such as interval timing or event counting. There are three registers that control the operation of T1: T1 Data Register (T1), T1 Mode Register (TMR), and T1 Prescale Register (PRE1). Because the timer, prescaler, and mode register are mapped into the standard Z8 register file, the software can treat the counter/timer as a generalpurpose register, thus eliminating the requirement for special instructions.
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T1 Data Register (T1) The counter/timer register (T1) consists of an 8-bit down counter, a write-only register that holds the initial count value, and a read-only register that holds the current count value. The initial value of T1 can range from 1 to 255 (0 represents 256) (see Table 34.)
Table 34. T1 Register [Group/Bank F0h, Register 2 (R242)] Bit Bit/Field R/W Reset 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T1_Value
R = Read, W = Write, X = Indeterminate Bit Position 76543210
Bit/Field T1 Value
R/W R W
Value Data Data
Description Current Value Initial Value (Range 1 to 256 Decimal)
T1 Mode Register (TMR) Under software control, T1 counter/timer is started and stopped using the T1 Mode Register as shown in Table 35.
Table 35. TMR Register [Group/Bank F0h, Register 1 (R241)] Bit Bit/Field R/W Reset Bit Position 76______ 7 6 5 4 3 T1_ Count R/W 0 2 T1_ Load R/W 0 1 0
TOUT_Mode R/W 0 R/W 0
TIN_Mode R/W 0 R/W 0
Reserved R/W 1 R/W 1
R = Read, W = Write, X = Indeterminate Bit/Field TOUT Mode R/W R/W Value 11 10 01 00 11 10 01 00 1 0 Description Internal Clock OUT on P56 T1OUT on P56 Reserved Not used (P56 configured as I/O) Trigger Input (Retriggerable) Trigger Input (Not-retriggerable) Gate Input External Clock Input (TIN on P52) Enable T1 Count Disable T1 Count
__54____
TIN Mode
R/W
____3___
T1 Count
R/W
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Table 35. TMR Register [Group/Bank F0h, Register 1 (R241)] (Continued) _____2__ ______10 T1 Load Reserved R/W R W 1 0 1 X Load T1 No effect Always reads 11 No effect
T1 Prescale Register (PRE1) The T1 prescaler consists of an 8-bit register and a 6-bit down-counter. The six most significant bits (D2-D7) of PRE1 hold the prescaler's count modulo, a value from 1 to 64 decimal, as shown in Table 36. The prescale register also contains control bits that specify the counting mode and clock source for T1.
Table 36. PRE1 Register [Group/Bank F0h, Register 3 (R243)] Bit Bit/Field R/W Reset Bit Position 765432__ _______1_ ________0 7 6 5 4 3 2 1 0
Prescaler_Modulo R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
Clock_ Count_ Source Mode R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field Clock Source Count Mode R/W R/W R/W Value Data 1 0 1 0 Description Range: 1 to 64 Decimal T1 Internal T1 External (TIN on P52) T1 Modulo-n T1 Single Pass
Prescaler Modulo R/W
Timer Control Registers--T8 and T16 Timers One of the unique features of the Z86D99/Z86L99 family is a special timer architecture to automate the generation and reception of complex pulses or signals. This timer architecture consists of one programmable 8-bit counter timer with two capture registers and two load registers and a programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair and their associated control registers. These counter/timers can work independently or can be combined together using a number of user-selectable modes governed by the T8/T16 control registers.
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T8/T16 Control Register A (CTR1) The T8/T16 Control Register A controls the functions in common with both the T8 and T16 counter/timers. The T8 and T16 counter/timers have two primary modes of operation: Transmit Mode and Demodulation Mode. Transmit Mode is used for generating complex waveforms. The Transmit Mode has two submodes: Normal Mode and Ping-Pong Mode. The settings for CTR1 in Transmit Mode are given in Table 37.
Table 37. CTR1 Register (In Transmit Mode) (Group/Bank 0Dh, Register 1) Bit 7 6 P43 Out R/W 0 5 4 3 2 1 0
Bit/Field R/W Reset Bit Position 7_______ _6______ __54____
Mode R/W 0
T8/T16_Logic R/W 0 R/W 0
Transmit_ Submode R/W 0 R/W 0
Initial_ Initial_ T16_ T8_Out Out R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field Mode P43_Out T8/T16 Logic R/W R/W R/W R/W Value 1 0 1 0 11 10 01 00 11 10 01 00 1 0 1 0 Description Demodulation Transmit P43 configured as T8/T16 Output P43 configured as I/O NAND NOR OR AND T16_Out = 1 T16_Out = 0 Ping-Pong Mode Normal Operation T8_Out set to 1 initially T8_Out set to 0 initially T16_Out set to 1 initially T16_Out set to 0 initially
____32__
Transmit_ Submode
R/W
______1_ _______0
Initial_T8_Out Initial_T16_Out
R/W R/W
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In Demodulation Mode, the T8 and T16 counter/timers are used to capture and demodulate complex waveforms. The settings for CTR1 in Demodulation Mode are given in Table 38.
Table 38. CTR1 Register (in Demodulation Mode) (Group/Bank 0Dh, Register 1) Bit Bit/Field R/W Reset Bit Position 7_______ _6______ __54____ 7 Mode R/W 0 6 5 4 3 2 1 Rising Edge R/W 0 0 Falling Edge R/W 0
Demod _Input Edge_Detect R/W 0 R/W 0 R/W 0
Glitch_Filter R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field Mode Demodulator_ Input Edge_Detect R/W R/W R/W R/W Value 1 0 1 0 11 10 01 00 11 10 01 00 1 0 1 0 1 0 1 0 Description Demodulation Transmit P20 as Demodulator Input P51 as Demodulator Input Reserved Both Edges Rising Edge Falling Edge 16 SCLK Cycles 8 SCLK Cycles 4 SCLK Cycles No Filter Rising Edge Detected No Rising Edge Reset Flag to 0 No Effect Falling Edge Detected No Falling Edge Reset Flag to 0 No Effect
____32__
Glitch_Filter
R/W
______1_
Rising_Edge
R R W W R R W W
_______0
Falling_Edge
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T8/T16 Control Register B (CTR3) The T8/T16 Control Register B, known as CTR3, is a new register to the Z86D99/ Z86L99 family. This register allows the T8 and T16 counters to be synchronized. The settings of CTR3 are described in Table 39.
Table 39. CTR3 Register (Group/Bank 0Dh, Register 3) Bit Bit/Field R/W Reset Bit Position 7_______ 7 6 5 4 3 2 1 0
T16_ T8_ Sync Enable Enable Mode R/W 0 R/W 0 R/W 0
Reserved R/W X R/W X R/W X R/W X R/W X
R = Read, W = Write, X = Indeterminate Bit/Field T16 Enable R/W R R W W R R W W R/W R W Value 1 0 1 0 1 0 1 0 1 0 1 X Description Counter Enabled Counter Disabled Enable Counter Stop Counter Counter Enabled Counter Disabled Enable Counter Stop Counter Enable Sync Mode Diable Sync Mode Always reads 11111 No Effect
_6______
T8 Enable
__5_____ ___43210
Sync Mode Reserved
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T8 Control Register (CTR0) As shown in Table 40, the T8 Control Register, known as CTR0, controls the operation of the 8-bit T8 timer.
Table 40. CTR0 Register (Group/Bank 0Dh, Register 0) Bit 7 6 5 4 3 2 1 0
Bit/Field R/W Reset Bit Position 7_______
Single/ T8_ ModTime_ Enable ulo-n Out R/W 0 R/W 0 R/W 0
T8_Clock R/W 0 R/W 0
Capture Counter INT_ INT_ P40_ Mask Mask Out R/W 0 R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field T8 Enable R/W R R W W R/W R R W W R/W Value 1 0 1 0 1 0 1 0 1 0 11 10 01 00 1 0 1 0 1 0 Description Counter Enabled Counter Disabled Enable Counter Stop Counter Single Pass Modulo-n Counter Timeout Occurred No Counter Timeout Reset Flag to 0 No Effect SCLK/8 SCLK/4 SCLK/2 SCLK Enable Data Capture Interrupt Disable Data Capture Interrupt Enable Time_Out Interrupt Disable Time_Out Interrupt P40 configured as T8 Output P40 configured as I/O
_6______ __5_____
Single/ Modulo-n Time_Out
___43___
T8 Clock
_____2__ ______1_ _______0
Capture Interrupt R/W Mask Counter Interrupt R/W Mask P40_Out R/W
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T8 High Capture Register (HI8) The T8 High Capture Register, as described in Table 41, holds the captured data from the output of the T8 counter/timer. This register is typically used to hold the number of counts when the input signal is high (or 1).
Table 41. HI8 Register (Group/Bank 0Dh, Register B) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T8_Capture_HI
R = Read, W = Write, X = Indeterminate Bit/Field T8 Capture High Value R/W R W Value Data Description Captured Data No Effect
T8 Low Capture Register (LO8) The T8 Low Capture Register, as described in Table 42, holds the captured data from the output of the T8 counter/timer. This register is typically used to hold the number of counts when the input signal is low (or 0).
Table 42. LO8 Register (Group/Bank 0Dh, Register A) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T8_Capture_LO
R = Read, W = Write, X = Indeterminate Bit/Field T8 Capture Low Value R/W R W Value Data Description Captured Data No Effect
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T8 High Load Register (TC8H) The T8 High Load Register, as described in Table 43, is loaded with the counter value necessary to keep the T8_Out signal in the high state for the required time.
Table 43. TC8H Register (Group/Bank 0Dh, Register 5) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T8_Level_HI
R = Read, W = Write, X = Indeterminate Bit/Field T8 Level High Value R/W R/W Value Data Description Duration that T8_Out remains High
T8 Low Load Register (TC8L) The T8 Low Load Register, as described in Table 44, is loaded with the counter value necessary to keep the T8_Out signal in the low state for the required time.
Table 44. TC8L Register (Group/Bank 0Dh, Register 4) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T8_Level_LO
R = Read, W = Write, X = Indeterminate Bit/Field T8 Level Low Value R/W R/W Value Data Description Duration that T8_Out remains Low
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T16 Control Register (CTR2) The T16 Control Register, known as CTR2, controls the operation of the 16-bit T16 timer (see Table 45).
Table 45. CTR2 Register (Group/Bank 0Dh, Register 2) Bit 7 6 5 4 3 2 1 0
Bit/Field R/W Reset Bit Position 7_______
Single/ T16_ ModTime_ Enable ulo-n Out R/W 0 R/W 0 R/W 0
T16_Clock R/W 0 R/W 0
Capture Counter INT_ INT_ P41_ Mask Mask Out R/W 0 R/W 0 R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field T16 Enable R/W R R W W R/W 1 0 1 0 __5_____ Time_Out R R W W R/W 1 0 1 0 11 10 01 00 1 0 1 0 1 0 Value 1 0 1 0 Description Counter Enabled Counter Disabled Enable Counter Stop Counter In Transmit Mode: Single Pass Modulo-n In Demodulation Mode: T16 Does Not Recognize Edge T16 Recognizes Edge Counter Timeout Occurred No Counter Timeout Reset Flag to 0 No Effect SCLK/8 SCLK/4 SCLK/2 SCLK Enable Data Capture Interrupt Disable Data Capture Interrupt Enable Time_Out Interrupt Disable Time_Out Interrupt P41 configured as T16 Output P41 configured as I/O
_6______
Single/ Modulo-n
___43___
T16 Clock
_____2__ ______1_ _______0
Capture Interrupt R/W Mask Counter Interrupt R/W Mask P41_Out R/W
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T16 MS-Byte Capture Register (HI16) The T16 MS-Byte Capture Register, as described in Table 46, holds the captured data from the output of the T16 counter/timer. This register holds the most significant byte of the data.
Table 46. HI16 Register (Group/Bank 0Dh, Register 9) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T16_Capture_HI
R = Read, W = Write, X = Indeterminate Bit/Field T16 Capture HI R/W R W Value Data Description MS-Byte of Captured Data No Effect
T16 LS-Byte Capture Register (LO16) The T16 LS-Byte Capture Register, as described in Table 47, holds the captured data from the output of the T16 counter/timer. This register holds the least significant byte of the data.
Table 47. LO16 Register (Group/Bank 0Dh, Register 8) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T16_Capture_LO
R = Read, W = Write, X = Indeterminate Bit/Field T16 Capture LO R/W R W Value Data Description LS-Byte of Captured Data No Effect
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T16 MS-Byte Load Register (TC16H) The T16 MS-Byte Load Register, as described in Table 48, is loaded with the most significant byte of the T16 counter value.
Table 48. TC16H Register (Group/Bank 0Dh, Register 7) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T16_Data_HI
R = Read, W = Write, X = Indeterminate Bit/Field T16 Data HI R/W R/W Value Data Description MS-Byte of the T16 Counter
T16 LS-Byte Load Register (TC16L) The T16 LS-Byte Load Register, as described in Table 49, is loaded with the least significant byte of the T16 counter value.
Table 49. TC16L Register (Group/Bank 0Dh, Register 6) Bit Bit/Field R/W Reset Bit Position 76543210 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 R/W 0
T16_Data_LO
R = Read, W = Write, X = Indeterminate Bit/Field T16 Data LO R/W R/W Value Data Description LS-Byte of the T16 Counter
Stop-Mode Recovery Control Registers The Z86D99/Z86L99 family of products allows 16 individual I/O pins (Ports 2 and 5) to be used as a stop-mode recovery sources. The STOP mode is exited when one of these SMR sources is toggled.
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Stop-Mode Recovery Register The SMR register serves two functions. Bit D7 of the SMR register, as shown in Table 50, is the Stop Mode Flag that is set upon entering stop mode. A 0 in this bit indicates that the device has been reset by a POR or WDT Reset. A POR or WDT Reset is sometimes referred to as a "cold" start. A 1 in bit D7 indicates that the device was awakened by a SMR source. Waking a device with a SMR source is sometimes referred to as a "warm" start. The Stop Mode Recovery source can be selected by any combination of P2 and P5 by P2SMR and P5SMR, respectively. If the pin is selected as the SMR source, its logic level is latched into a register. A wait up signal is generated if its logic level changes. This applies to all selected pins for the SMR source. The comparators of P5 cannot be used as an SMR source. The comparator is turned off in STOP mode.
Table 50. SMR Register (Group/Bank 0Fh, Register B) Bit Bit/Field R/W Reset Bit Position 7_______ 7 Stop Flag R 0 6 5 4 3 2 1 0
ReStop served Delay R/W 0 W 1
Reserved R/W 0 R/W 0 R/W 0
SCLK Select W 0 W 0
R = Read, W = Write, X = Indeterminate Bit/Field Stop Mode Flag R/W R R W R W R W W R W R W W W W Value 1 0 X 1 X 1 1 0 1 X 11 11 10 01 00 Description Stop Recovery (warm start) POR/WDT Reset (cold start) No Effect Always reads 1 No Effect Always reads 1 Enable 5ms /Reset delay Disable /Reset delay after SMR Always reads 111 No Effect Always reads 11 SCLK, TCLK = XTAL/16 SCLK, TCLK = XTAL SCLK, TCLK = XTAL/32 SCLK, TCLK = XTAL/2
_6______ __5_____
Reserved Stop Delay
___432__ _______10
Reserved System Clock Select
The second function of the SMR register is the selection of the external clock divide value. The purpose of this control is to selectively reduce device power
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consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers and interrupt logic). Port 2 Stop Mode Recovery (P2SMR) The P2SMR register, as described in Table 51, defines which I/O lines in Port 2 are to be used as stop mode recovery sources.
Table 51. P2SMR Register (Group/Bank 0Fh, Register 1) Bit Bit/Field R/W Reset Bit Position 76543210 (by bit) 7 P27RS R/W 0 6 P26RS R/W 0 5 P25RS R/W 0 4 P24RS R/W 0 3 P23RS R/W 0 2 P22RS R/W 0 1 P21RS R/W 0 0 P20RS R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field R/W Value 1 0 Description Recovery Source Not
Port 2 Stop Mode R/W Recovery
Port 5 Stop-Mode Recovery (P5SMR) The P5SMR register, as described in Table 52, defines which I/O lines in Port 5 are to be used as stop-mode recovery sources.
Table 52. P5SMR Register (Group/Bank 0Fh, Register 5) Bit Bit/Field R/W Reset Bit Position 76543210 (by bit) 7 P57RS R/W 0 6 P56RS R/W 0 5 P55RS R/W 0 4 P54RS R/W 0 3 P53RS R/W 0 2 P52RS R/W 0 1 P51RS R/W 0 0 P50RS R/W 0
R = Read, W = Write, X = Indeterminate Bit/Field R/W Value 1 0 Description Recovery Source Not
Port 5 Stop Mode R/W Recovery
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Electrical Characteristics
This section covers the absolute maximum ratings, standard test conditions, DC characteristics, and AC characteristics.
Absolute Maximum Ratings
Table 53 lists the absolute maximum ratings.
Table 53. Absolute Maximum Ratings Symbol VMAX TSTG TA VRAM
Note:
Description Supply Voltage (*) Storage Temp. Oper. Ambient Temp. Minimum RAM Voltage
Min -0.3 -65 1.0 V**
Max +7.0 +150
Units V C C
*Voltage on all pins with respect to GND. See "Ordering Information" on page 95. ** Estimated value, not tested.
Stresses greater than those listed in the preceding table can cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period can affect device reliability.
Standard Test Conditions
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to GND. Positive current flows into the referenced pin (see Figure 36).
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From Output Under Test
I
150pF
Figure 36. Test Load Diagram
DC Characteristics
Table 54 lists the DC characteristics for the Z86D99X (OTP only). Table 55 lists the DC characteristics for the Z86L99X (mask only).
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Table 54. DC Characteristics for the Z86D99X (OTP Only)
Symbol VDD VCH VCL VIH VIL VOH1 VOH2 VOL1 VOL2 ICCO IIL ICC Parameter Power Supply Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Regular I/O High Drive Pins (P54, P55, P56, P57) Regular I/O Output low voltage High Drive Pins (P54, P55, P56, P57) Controlled Current Output (P43) Input Leakage Supply Current 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 3.0 V 5.5 V 70 70 -1 -1 VDD Min 3 0.8Vdd 0.8Vdd Vss-0.3 Vss-0.3 0.7Vdd 0.7Vdd Vss-0.3 Vss-0.3 VDD-0.8 VDD-0.8 VDD-0.8 VDD-0.8 0.4 0.8 0.4 0.8 120 120 1 A 1 A 10 15 250 850 3 5 2 4 20 30 Max 5.5 Vdd+0.3 Vdd+0.3 0.2Vdd 0.2Vdd Vdd+0.3 Vdd+0.3 0.2Vdd 0.2Vdd V V V V V V V V V V V V mA mA A A mA mA A A mA mA mA mA A A -1.2 mA -5.0 mA 2 mA 4.0 mA 4 mA 7.0 mA Vout = 1.2 V to VDD (see Figure 17) Vin=0 V, Vdd Vin=0 V, Vdd at 8 MHz at 8 MHz at 32 KHz at 32 KHz ADC is off. Vin=0 V, Vdd at 8 MHz Clock divided by 16 XTAL running ADC is off.
Vin=0 V, Vdd; ADC is off. P43=1 or high impedance WDT, Comparators, Low Voltage Detection, and ADC (if applicable) are disabled. The IC might draw more current if any of the above peripherals is enabled.
Units V V
Comments Driven by Ext. clock generator Driven by Ext. clock generator
ICC1
Standby Current (Halt Mode)
ICC2
Standby Current (STOP Mode)
IADC VLV
Current with A/D Running Vdd Low-Voltage Protection
3.0 V 5.5 V
500 900 2.90
A A V Low voltage protection is also known as brownout. Typical is 2.6 V.
VLB
Low-Battery Detection
VLV+ 0.5
V V
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Table 55. DC Characteristics for the Z86L99X (Mask Only)
Symbol VDD VCH VCL VIH VIL VOH1 Parameter Power Supply Voltage Clock Input High Voltage Clock Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Regular I/O 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V VOH2 High Drive Pins (P54, P55, P56, P57) 2.3 V 5.5 V 2.3 V 5.5 V VOL1 Regular I/O Output low voltage 2.3 V 5.5 V 2.3 V 5.5 V VOL2 High Drive Pins (P54, P55, P56, P57) 2.3 V 5.5 V 2.3 V 5.5 V ICCO IIL ICC Controlled Current Output (P43) Input Leakage Supply Current 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 70 70 -1 -1 VDD Min 2.3 0.8Vdd 0.8Vdd Vss-0.3 Vss-0.3 0.7Vdd 0.7Vdd Vss-0.3 Vss-0.3 2.0 5.0 1.9 5.0 1.9 5.1 1.7 4.7 0.4 V 0.4 V 0.8 V 0.8 V 0.4 V 0.4 V 0.8 V 0.8 V 120 120 1 A 1 A 3 8 250 850 2 5 8 25.0 Max 5.5 Vdd+0.3 V Vdd+0.3 V 0.2Vdd 0.2Vdd Vdd+0.3 V Vdd+0.3 V 0.2Vdd 0.2Vdd V V V V V V V V V V V V V V V V V V mA mA A A mA mA A A mA mA A A -0.5 mA -1.2 mA -3 mA -5 mA 2 mA 4 mA 4 mA 7 mA Vout = 1.2 V to VDD at room temperature (see Figure 17) Vin=0 V, Vdd Vin=0 V, Vdd at 8 MHz at 8 MHz at 32 KHz at 32 KHz ADC is off. Vin=0 V, Vdd at 8 MHz
Vin=0 V, Vdd;ADC is off. WDT, Comparators, Low Voltage Detection, and ADC (if applicable) are disabled. The IC might draw more current if any of the above peripherals is enabled. at 30 C
Units
Comments Driven by Ext. clock generator Driven by Ext. clock generator
ICC1 ICC2
Standby Current (Halt Mode) Standby Current (STOP Mode)
ICC2 ILV IADC VLV VLB
Standby Current (STOP Mode) Standby Current (Low Voltage) Current with A/D Running Vdd Low-Voltage Protection Low-Battery Detection
5.5 V 2.3 V 5.5 V
15 20 500 900 2.2 3.0
A A A A V V
Measured at VDD=VLV-0.2 V.
Low voltage protection is also known as brownout. Typical is around 1.7 V at room temperature. Typical is around 2.4 V at room temperature.
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Analog-to-Digital Converter Characteristics
Table 56 lists the analog-to-digital converter characteristics.
Table 56. Analog-to-Digital Converter Characteristics Parameter
Resolution
Minimum Typical 8 0.5 0.5
Maximum
Units bits
Integral Nonlinearity Differential Nonlinearity Zero Error at 25 C Supply Voltage Range (OTP) 3.0 Supply Voltage Range (ROM) 2.3 Power Dissipation (No Load) Clock Frequency (f ADC) Input Voltage Range Step Response ADC Input Capacitance Vref Input Capacitance VRef+ Range VRef- Range (VRef+)-(VRef-) Temperature Range 3-db Frequency Signal to Noise ADC Output Code Vref Input Source Impedance ADC Input Source Impedance 47 25 25 VRef-+2.0 AGND 2.0 0 VRef-
1 1 7.8 5.5 5.5 1.2 4 VRef+ 40 40 AVDD VRef+-2.0 AVDD 70
LSB LSB mV V V mW MHz V
2/(0.0021 X f ADC) s pF pF V V V C Hz db Dout 1.0 1.0 kOhms kOhms
(0.0021 X f ADC)
Notes: Dout= [(Vin-VRef-)/(VRef+-VRef-)] X 256 f ADC = set in ADCCTRL configuration register Step Response is the time to track the input if a step from VRef- to VRef+ is applied.
The ADC input is a switching capacitor that charges up to the applied input voltage whenever it is configured as an ADC input. If you switch it from digital mode to
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the ADC input mode, the switching capacitor starts to charge up from 0 V. For the maximum swing (Dout = 0 to FF), it takes 2/(0.0021x f ADC). For an 8-MHz MCU crystal (with clock divide-by-two mode), the internal system clock is 4 MHz. In ADCCTRL, if you select the ADC frequency = system clock divided by 1 option, f ADC = 4 MHz. The step response = 238 uS.
AC Characteristics
Table 57 lists the AC characteristics.
Table 57. AC Characteristics No. Symbol 1 2 3 4 5 6 7 8 9 10 12 TpC TrC, TfC TwC TwTinL TwTinH TpT1in TrTin, TfTin TwIL TwIH Twsm Twdt Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer 1 Input Period Timer Input Rise and Fall Time Interrupt Request Low Time VDD 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 2.3 V 5.5 V 100 70 5 5 12 12 25 10 5.0 5.0 2TPC 2TPC 2 2 8 8 100 100 Min 120 120 Max DC DC 25 ns 25 ns ns ns ns TpC TpC TpC TpC ns ns ns ns TpC TpC ns ns ms ms Units ns
Interrupt Request Input High Time 2.3 V 5.5 V Stop-Mode Recovery Width Spec Watch-Dog Timer Time Out 2.3 V 5.5 V 2.3 V 5.5 V
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Packaging
Figure 37 through Figure 40 show the available packages.
D
48 25
c
E
H
1
24 Detail A
A2 A1
A
CONTROLLING DIMENSIONS : MM LEADS ARE COPLANAR WITHIN .004 INCH
SEATING PLANE e b
L 0-8
Detail A
Figure 37. 48-Pin SSOP
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Figure 38. 40-Pin PDIP
Figure 39. 28-Pin PDIP
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Figure 40. 28-Pin SOIC
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Design Considerations
The Z8 uses a Pierce oscillator with an internal feedback circuit. The advantages of this circuit are low cost, large output signal, low-power level in the crystal, stability with respect to VCC and temperature, and low impedances (not disturbed by stray effects.) One drawback is the requirement for high gain in the amplifier to compensate for feedback path losses. Traces connecting crystal, capacitors, and the Z8 oscillator pins must be as short and wide as possible. Short and wide traces reduce parasitic inductance and resistance. The components (capacitors, crystal, and resistors) must be placed as close as possible to the oscillator pins of the Z8. The traces from the oscillator pins of the integrated circuit (IC) and the ground side of the lead capacitors must be guarded from all other traces (clock, VCC, and system ground) to reduce cross-talk and noise injection. Guarding the traces is usually accomplished by keeping other traces and system ground trace planes away from the oscillator circuit and by placing a Z8 device VSS ground ring around the traces/components. The ground side of the oscillator lead capacitors must be connected to a single trace to the Z8 VSS (GND) pin. It must not be shared with any other system ground trace or components except at the Z8 device VSS pin. Not sharing the ground side of the oscillator lead capacitors is to prevent differential system ground noise injection into the oscillator.
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Ordering Information
Part Z86D99 (OTP) PSI Z86D990PZ008SC Z86D990HZ008SC Z86D991PZ008SC Z86D991SZ008SC Z86L990PZ008SC Z86L990HZ008SC Z86L991PZ008SC Z86L991SZ008SC Z86L996PZ008SC Z86L996SZ008SC Z86L997PZ008SC Z86L997SZ008SC Z86L9900100ZEM Z86D9900100ZDH Z86L9900100ZCO Description 40-pin PDIP 48-pin SSOP 28-pin PDIP 28-pin SOIC 40-pin PDIP 48-pin SSOP 28-pin PDIP 28-pin SOIC 28-pin PDIP 28-pin SOIC 28-pin PDIP 28-pin SOIC Emulator/Programmer 48 SSOP Adapter Evaluation Board
Z86L99 (Mask ROM)
Emulator Adapter Evaluation Board
For fast results, contact your local ZiLOG sale offices for assistance in ordering part(s). Updated information can be found on the ZiLOG website:
HTTP://WWW.ZILOG.COM
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or nonconformance with some aspects of the document might be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield issues. ZiLOG, Inc. 532 Race Street San Jose, CA 95126-3432 Telephone: (408) 558-8500 FAX: 408 558-8300 Internet: HTTP://WWW.ZILOG.COM
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